公开(公告)号：JPH0529381A

公开(公告)日：1993-02-05

申请号：JP17702691

申请日：1991-07-17

Applicant: TOSHIBA CORP

Inventor： MATSUKI KOJI ,  TOTOKI TAKASHI

IPC: H01L21/60

Abstract: PURPOSE:To prevent, as much as possible, a latch up. CONSTITUTION:First bumps 3a are formed on the first surface 1a on which a semiconductor chip l is formed, and second bumps 3b are formed on a second surface 1b opposite to the first surface. First leads 6, to be bonded to the first bumps, are formed on one surface of a film carrier tape 4, whilst second leads 7, to be bonded to the second bumps, are formed on the other surface of the film carrier tape. The first bumps 3a and the first leads 6 are bonded together, and the second bumps 3b and the second leads 7 are bonded together.

公开(公告)号：JPS62151775A

公开(公告)日：1987-07-06

申请号：JP29453585

申请日：1985-12-26

Applicant: TOSHIBA CORP

Inventor： TOTOKI TAKASHI

IPC: H03K19/00 ,  G01R31/28

Abstract: PURPOSE:To set an optional test mode with one terminal by cascading shift registers, supplying a repetitive signal having a specific pattern to the register in the initial stage, and outputting a signal corresponding to the pattern from a gate circuit. CONSTITUTION:Circuits 6 and 7 are NOR gates, the input terminal of the circuit 6 is connected to Q terminals of registers 1-4, and the input terminal of the circuit 7 is connected to Q terminals of the circuit 7. Therefore, a mode signal from the circuit 6 is at an H level only when a signal indicating an L level at any time is inputted and a mode signal from the circuit 7 is at the H level only when a signal indicating the H level at any time is inputted. A circuit 8 is a composite circuit of two four-input AND gates and one OR gate and circuits 9-11 are composite circuits of four four-input AND gates and one four-input OR gate 1; and those circuits are so constituted as to have the H level only when a specific repetitive signal is inputted. For the purpose, an input pattern from one external terminal 5 is selected to set, for example, six kinds of specific test mode signals optionally.

公开(公告)号：JPS5776928A

公开(公告)日：1982-05-14

申请号：JP15193480

申请日：1980-10-29

Applicant: Toshiba Corp

Inventor： KAWAKAMI SUSUMU ,  TOTOKI TAKASHI

IPC: H03K23/58 ,  H03K23/00

CPC classification number: H03K23/58

Abstract: PURPOSE:To obtain a plurality of outputs mutually synchronized, by providing D type flip-flops taking the basic clock as a clock input and a counter output as a D input, in the asynchronous counter consisting of D type flip-flops. CONSTITUTION:A counter is constituted by using a plurality of D type flip-flops, taking the prestage output Q1' as the clock input of the next stage, and the output Q1 of each stage as the D input of the stage. A D type flip-flop D-FFM1 taking the output QM of the M-th stage D type flip-flop D-FFM as the D input, and a D type flip-flop D-FFN1 taking the Nth stage of output QN as the D input are provided, and an output synchronized with the basic clock CK is obtained by taking out the OR logic of the outputs QM1, QN1 as an output OUT2 and taking the basic clock CK as the clock input.

Abstract translation: 目的：为了获得相互同步的多个输出，通过提供将基本时钟作为时钟输入的D型触发器和作为D输入的计数器输出，在由D型触发器组成的异步计数器中。 构成：使用多个D型触发器构成计数器，将前级输出Q1'作为下一级的时钟输入，将各级的输出Q1作为该级的D输入。 将第M级D型触发器D-FFM的输出QM作为D输入的AD型触发器D-FFM1和以输出QN为第N级的D型触发器D-FFN1为 D输入，并且通过取出输出QM1，QN1的OR逻辑作为输出OUT2并且以基本时钟CK作为时钟输入，获得与基本时钟CK同步的输出。

公开(公告)号：JPS6457736A

公开(公告)日：1989-03-06

申请号：JP21431187

申请日：1987-08-28

Applicant: TOSHIBA CORP

Inventor： TOTOKI TAKASHI

IPC: H01L21/3205 ,  H01L21/82 ,  H01L23/52

Abstract: PURPOSE:To lay out wirings for other signals easily by assigning a wiring as an uppermost layer formed onto approximately the whole surface of a chip as a wiring for an arbitrary signal such as a system clock in a semiconductor integrated circuit with multilayer metallic interconnections. CONSTITUTION:In a CMOS integrated circuit having three-layer aluminum wiring structure, an aluminum wiring 21 as an uppermost layer is evaporated and formed onto approximately the whole surface on a chip, assigned as a wiring such as a system clock wiring, and brought into contact with a signal wiring 19 requiring clock supply in second layer wirings. Since the wiring resistance of the metallic wiring 21 shaped onto approximately the whole surface on the chip is reduced extremely, the metallic wiring 21 is particularly proper when it is used as the system clock wiring, etc., supplying a system clock for synchronously operating the whole integrated circuit.

公开(公告)号：JPS59181644A

公开(公告)日：1984-10-16

申请号：JP5608683

申请日：1983-03-31

Applicant: Toshiba Corp

Inventor： MORI TOSHIAKI ,  KODAMA YASUYOSHI ,  TOTOKI TAKASHI

IPC: H01L21/822 ,  H01L21/82 ,  H01L27/02 ,  H01L27/04 ,  H01L27/118

CPC classification number: H01L27/0207

Abstract: PURPOSE:To vary and correct a function in a short time at low cost by forming a contact hole, a first layer metallic wiring and a through-hole when a two layer metallic wiring forming process is adopted to an activ element in a basic cell coalesced body not used, which need not be connected. CONSTITUTION:When constituting a predetermined functional circuit, a hole and a wiring, such as a contact hole 15, a first layer aluminum wiring 14 and a through-hole 17 are each formed to a basic cell to which the first layer aluminum wiring 14 and a second layer aluminum wiring must be executed, and the contact hole 15, the first layer aluminum wiring 14 and the through-hole 17 are also shaped severally at prescribed positions to a basic cell, to which the second layer aluminum wiring need not be executed and which is not used originally. Accordingly, only a mask for forming the second layer aluminum wiring as a final process for the formation of the wirings may be corrected.

Abstract translation: 目的：通过形成接触孔来在短时间内以低成本改变和校正功能，当对基础细胞中的活性成分采用双层金属布线形成工艺时，第一层金属布线和通孔聚结 身体不用，不需要连接。 构成：在构成规定的功能电路时，分别形成有接触孔15，第一层铝布线14和通孔17等的孔和布线，其中，第一层铝布线14和 必须执行第二层铝布线，并且接触孔15，第一层铝布线14和通孔17也在规定位置分别形成到不需要执行第二层铝布线的基本单元 并且最初没有使用。 因此，可以仅修正用于形成第二层铝布线的掩模，作为形成布线的最终方法。

公开(公告)号：JPS5910028A

公开(公告)日：1984-01-19

申请号：JP11794282

申请日：1982-07-07

Applicant: Toshiba Corp

Inventor： TOTOKI TAKASHI ,  KAWAKAMI SUSUMU

IPC: H03K12/00 ,  H03K3/03 ,  H03K17/687 ,  H03K19/0175

CPC classification number: H03K3/0307

Abstract: PURPOSE:To avoid consumption of the undesired current, by increasing and decreasing the mutual conductance of an inverter which is set to the oscillating frequency of a signal generating circuit in response to the frequency of a clock signal. CONSTITUTION:An inverter 2 is designed to the minimum mutual conductance gm that is driven by a frequency obtained while a signal generating circuit is working. A clocked inverter 6 is designed to a high mutual conductance gm which can work even with a clock pulse of a higher frequency supplied from a joint 5. In the case of a normal operation performed by the signal generating circuit, the inverter 6 is nonconductive due to a control signal 7. Then the inverter 6 conducts with the signal 7 when a clock pulse of a frequency higher than the inner oscillating frequency is applied to the joint 5. Thus both inverters 2 and 6 have operations parallel to each other. This can increase the mutual inductance gm of a waveform shaping inverter and therefore avoid the useless consumption of current.

Abstract translation: 目的：通过响应于时钟信号的频率，增加和减少设置在信号发生电路的振荡频率的逆变器的互导，以避免消耗不需要的电流。 构成：逆变器2被设计为由信号发生电路工作时获得的频率驱动的最小互导gm。 时钟反相器6被设计成高互导gm，甚至可以用从接头5提供的较高频率的时钟脉冲进行工作。在由信号发生电路执行的正常操作的情况下，逆变器6是不导通的 然后当频率高于内部振荡频率的时钟脉冲被施加到接头5时，反相器6与信号7进行导通。因此两个逆变器2和6具有彼此平行的操作。 这可以增加波形整形逆变器的互感gm，从而避免无用的电流消耗。

公开(公告)号：JPS5776927A

公开(公告)日：1982-05-14

申请号：JP15193380

申请日：1980-10-29

Applicant: Toshiba Corp

Inventor： KAWAKAMI SUSUMU ,  TOTOKI TAKASHI

IPC: H03K23/00 ,  H03K23/58

CPC classification number: H03K23/588

Abstract: PURPOSE:To obtain a stable output synchronized with a basic clock, by providing a D type flip-flop to which the basic clock is inputted between stages of a counter, in the asynchronous counter consisting of D type flip-flops. CONSTITUTION:A plurality of D type flip-flop are used, and a counter is constituted by taking an output Q1' of the prestage as an input phi of the clock of the next stage and an output Q1 of each stage as the D input of the stage. Between a D type flip-flop D-FFN of the Nth stage and a D type flip-flop D-FFN+1 at the N+1th stage, a D type flip-flop D-FFM taking the Nth output as D input and the basic clock CP as a clock input phi is inserted. The shift in output delay time caused by dispersion of characteristics of each D type flip-flop circuit element is corrected to obtain an output synchronized with the basic clock CP.

Abstract translation: 目的：通过在由D型触发器组成的异步计数器中提供在计数器的各级之间输入基本时钟的D型触发器来获得与基本时钟同步的稳定输出。 构成：使用多个D型触发器，并且通过将前级的输出Q1'作为下一级的时钟的输入phi和各级的输出Q1作为D输入来构成计数器 舞台。 在第N级的D型触发器D-FFN和N + 1级的D型触发器D-FFN + 1之间，以N输出为D输入的D型触发器D-FFM和 插入作为时钟输入phi的基本时钟CP。 校正由每个D型触发器电路元件的特性偏差引起的输出延迟时间的偏移，以获得与基本时钟CP同步的输出。

公开(公告)号：JPS58182913A

公开(公告)日：1983-10-26

申请号：JP6659282

申请日：1982-04-21

Applicant: Toshiba Corp

Inventor： TOTOKI TAKASHI ,  SAKAMOTO HIROSHI

IPC: H03K5/08 ,  H03K5/24

CPC classification number: H03K5/249

Abstract: PURPOSE:To stabilize an input and an output potential and to reduce current consumption while decreasing the number of elements, by feeding the output of an amplifying circuit back to its input side positively after two signals are outputted from an input circuit. CONSTITUTION:When transfer gates G1 and G2 turn on and the 1st signal is outputted from the input signal 11, a voltage V1 is impressed to the input-side point (a) of a capacitor 12 and a voltage generated when the input and output terminals of an amplifying circuit 13 are short-circuited is impressed to the output-side point (b) to supply their difference voltage to the point (b). Once the gates G1 and G2 turn off, the gate G2 turns on and when the 2nd signal is outputted from the circuit 11, the voltage at the point (a) varies to V2 to output an amplification output with the difference voltage between both input signals to a point (c). Then, transistors (TR) 22 and 25 of the feedback circuit 14 turn on to put the inverter consisting of TRs 23 and 24 in operation. Its feedback operation is positive feedback operation, so the input and output potentials of the amplifying circuit 13 are stabilized. In addition, an MOSFET19 or 20 is cut off completely, so the current consumption is reduced.

Abstract translation: 目的：通过在从输入电路输出两个信号之后，将放大电路的输出反馈到其输入端，稳定输入和输出电位并减少电流消耗，同时减少元件数量。 构成：当传输门G1和G2导通并且从输入信号11输出第一信号时，电压V1被施加到电容器12的输入侧点（a）和当输入和输出端子 放大电路13的短路被施加到输出侧点（b）以将它们的差值电压提供给点（b）。 一旦门G1和G2关闭，门G2接通，当从电路11输出第二信号时，点（a）的电压变为V2，以输出两个输入信号之间的差分电压的放大输出 到（c）点。 然后，反馈电路14的晶体管（TR）22和25导通，使由TR 23和24组成的逆变器工作。 其反馈操作是正反馈操作，因此放大电路13的输入和输出电位稳定。 此外，MOSFET19或20被完全切断，因此电流消耗降低。

公开(公告)号：JPS61247984A

公开(公告)日：1986-11-05

申请号：JP8997785

申请日：1985-04-26

Applicant: TOSHIBA CORP

Inventor： TOTOKI TAKASHI ,  NAKAMURA MAKOTO

IPC: H03K3/78 ,  G01R31/28 ,  G01R31/317 ,  G01R31/3185

Abstract: PURPOSE:To decrease the number of external terminals necessary for a test and to set an optional test mode freely from outside by inputting specific pattern data to a terminal and generating two kinds of test mode signals, and increasing the number of connections of the shift register in a data shifting circuit. CONSTITUTION:Only one external terminal 16 is provided for a test circuit and the specific pattern data Din is inputted to this terminal 16 to generate two kinds of test mode signals M1 and M2, so the number of external terminals is decreased to one although two terminals are used conventionally. Further, the number of connections of the shift register in the data shifting circuit 15 is increased to increase the number of kinds of test mode signals and an optional test mode is set freely from outside by using only one external terminal.

公开(公告)号：JPS6155942A

公开(公告)日：1986-03-20

申请号：JP17802384

申请日：1984-08-27

Applicant: Toshiba Corp

Inventor： MATSUMOTO KEIJI ,  TOTOKI TAKASHI

IPC: H01L21/822 ,  H01L21/82 ,  H01L27/04 ,  H01L27/118

CPC classification number: H01L27/11807

Abstract: PURPOSE:To enhance number of gates practically by forming gate electrodes and impurity regions in a wiring region by use of a layer which does not influence upon the wiring and forming transistors in the wiring region by using said impurity regions as source and drain regions. CONSTITUTION:The semiconductor device of master slice system comprises the general-purpose cell arranging regions (a) and wiring regions (b) arranged among said regions (a). In the wiring region (b), layers 1, 1B,..., and nB are formed as gate electrodes and l pieces of N type impurity regions N1, N2,..., and Nl and P type impurity regions P1, P2,..., and Pl are formed under the layers 1, 1B,..., and nB. By using those impurity regions as source and drain regions, N-channel MOS transistors and P channel MOS transistor are formed in the wiring regions (b) thereby composing a CMOS circuit.

Abstract translation: 目的：通过使用不影响布线的层和通过使用所述杂质区作为源区和漏区在布线区中形成晶体管，在布线区域中形成栅电极和杂质区，实际上增加栅数。 构成：主片系统的半导体器件包括布置在所述区域（a）中的通用单元布置区域（a）和布线区域（b）。 在布线区域（b）中，形成层1，1B，...，nB作为栅电极和1个N型杂质区域N1，N2，...，N1和P型杂质区域P1，P2 ，...，和P1形成在层1,1B，...和nB之下。 通过使用这些杂质区域作为源极和漏极区域，在布线区域（b）中形成N沟道MOS晶体管和P沟道MOS晶体管，从而构成CMOS电路。