公开(公告)号：JPH0795163A

公开(公告)日：1995-04-07

申请号：JP23393193

申请日：1993-09-20

Applicant: TOSHIBA CORP

Inventor： MATSUSHIMA TOMOKO ,  NAKAJIMA NOBUYASU ,  MURAKAMI JUNZO

IPC: H04L1/00 ,  H04B14/04

Abstract: PURPOSE:To provide the data transmitter in which data are efficiently sent against a periodic error. CONSTITUTION:The transmitter is provided with a coding means 1 coding an information series to obtain a transmission data series, a transmission means 3 sending the transmission data series to a receiver side, a decoding means 5 receiving the signal sent by the transmission means 3 and decoding the received signal into a decoded data series, and error timing estimate means 6, 7 receiving at least one of the reception signal, the decoded data series, and output from the decoding means 5 other than the decoded data series to estimate a timing when an error takes place in the received signal, and at least one of the decoding and coding methods is corrected based on an error timing estimated by the error timing estimate means 6, 7.

公开(公告)号：JPH0774655A

公开(公告)日：1995-03-17

申请号：JP22033493

申请日：1993-09-03

Applicant: TOSHIBA CORP

Inventor： MATSUSHIMA TOMOKO

IPC: H03M13/00

Abstract: PURPOSE:To enable high-speed processing and make the device with a simple circuitry by parallely processing the P-symbol information. CONSTITUTION:The device is provided with a division means 3 dividing the K information symbol collection W={Wn-1, Wn-2...W0} into a part collection shown by a formula I of P (P is an integer higher than 2), P division calculation circuits 5 and 7 obtaining the division dividing the P part information polynomial expression shown by the formula II which takes the information symbol divided into P part collections as each coefficient by the generated polynomial expression G(X), and addition circuit 9 adding the output of the circuits 5 and 7. In this case, the information symbol is divided into two part collections and the parallel processing with two symbols is performed. Thus, as an error correction encoding device 1 can perform the parallel processing with two symbols, its processing is the double speed of the conventional error correcting encoding device. In this case, the information symbol is divided into two part collections and the parallel processing by two symbols is performed. Thus, as the error correction encoding device 1 can perform the parallel processing by two symbols, it can perform the processing at the double speed of the conventional device.

公开(公告)号：JPH0787143A

公开(公告)日：1995-03-31

申请号：JP22481193

申请日：1993-09-09

Applicant: TOSHIBA CORP

Inventor： MATSUSHIMA TOMOKO ,  NAKAMURA MAKOTO

IPC: H03M13/00 ,  H04L27/18

Abstract: PURPOSE:To improve reliability and to reduce envelope variance by removing corresponding values of phases, which are shifted from the phase selected by a modulating means by about 180 deg. or 0 deg., from continuously given values. CONSTITUTION:Two bits of transmission information are supplied to an r=2/log27 trellis encoding part 3. The encoding part 3 adds a redundancy to transmission information and supplies 7 values (three bits) to art 8 value differential encoder 5. At this time, data supplied to the encoder 5 is 7 values 0 to 7 except 4. The encoder 5 calculates the sum of modulus 8 between data outputted as the preceding conversion value and next supply data from the encoding part 3 and supplies it to a BPSK modulator 7, and 8 phases are selected in accordance with data from the encoder 5, and the signal modulated by these phases is outputted. Consequently, the variance in amplitude of the envelope is reduced, and the reliability of transmission information is improved because Viterbi decoding corresponding to trellis encoding is performed at the time of demodulation.

公开(公告)号：JPH07183862A

公开(公告)日：1995-07-21

申请号：JP32486993

申请日：1993-12-22

Applicant: TOSHIBA CORP

Inventor： MATSUSHIMA TOMOKO ,  SERIZAWA MUTSUMI ,  OGURA KOJI ,  NAKAJIMA NOBUYASU

IPC: H04L1/00 ,  H04J1/00 ,  H04J11/00 ,  H04L27/18

Abstract: PURPOSE:To realize an error correcting method where the speed-up of transmission speed is easy and the degradation of the error ratio of a frequency selective phasing is small, in an FDM transmission system. CONSTITUTION:A transmitter 301 is composed of (n) error correction encoders 101-1 to 101-n (n is >=2) performing an error correction encoding for transmission data, a mapping circuit 102 outputting m of data arranged so as to disperse each of n encoded data sequence on a frequency axis or a time axis and an FDM modulator 103 outputting signal where m of data is modulated into each of m carrier waves and is multiplexed. Therefore, plural error correction encoders 101-1 to 101-n and a decoder are provided, the application of high transmission speed to a system is easy. Because the burst error by a selective fading is effectively dispersed by a mapping means, the reliability of decoded data is improved. When a user receives only part of data in a multiconnection and a broadcasting system, the miniaturization of a receiver and low power consumption is performed.

公开(公告)号：JPH06276106A

公开(公告)日：1994-09-30

申请号：JP5856293

申请日：1993-03-18

Applicant: TOSHIBA CORP

Inventor： MATSUSHIMA TOMOKO

IPC: H03M13/00 ,  H03M13/15 ,  H03M13/37

Abstract: PURPOSE:To obtain a device which quicken a processing with small power consumption and a small circuit scale and can easily be applied to a multiple code by using an erroneous position polynomial calculation circuit by time division multiplexing. CONSTITUTION:Reception signals 11 to 13 inputted from input terminals 1a to 1c are respectively provided for delay circuits 2a to 2c and a syndrome calculation circuit 3. The outputs S1 and S2 of the circuit 3 are delivered to a erroneous position polynomial calculation circuit 4 and the coefficient of an erroneous position polynomial are calculated with sigma0 and sigma1. The coefficients sigma0 and sigma1 are provided for an erroneous position detection circuit 5 and flag signals F1 to F3 are provided for an error correcting circuit 6 to correct the errors of the reception signals outputted from circuits 2a to 2c. The reception signals whose errors are corrected are outputted from output terminals 7a to 7c by every three symbols in parallel to restore the three symbols in parallel. Consequently, codes can be decoded at triple processing speed with low power consumption and a small circuit scale.

公开(公告)号：JPH06204895A

公开(公告)日：1994-07-22

申请号：JP34895692

申请日：1992-12-28

Applicant: TOSHIBA CORP

Inventor： NAKAJIMA NOBUYASU ,  MATSUSHIMA TOMOKO

IPC: H04L1/00 ,  H03M13/23 ,  H03M13/41 ,  H04L25/08 ,  H03M13/12

Abstract: PURPOSE:To lower a decoding error rate by smoothing envelope information related to reception signals, increasing the reliability of branch metric and adding prescribed metric obtained by using a part or all of composite information further to pass metric. CONSTITUTION:The soft judgement information of soft judged reception signals is inputted to an input terminal Ta and the envelope information of the reception signals is inputted to the input terminal Tb. The envelope information of the reception signals inputted from the input terminal Tb is inputted to a smoothing circuit 1, smoothed and supplied to a branch metric calculation circuit along with the reception signals inputted from the input terminal Ta. Also, the branch metric is added to the pass metric of a previous stage stored in a pass metric storage means provided inside an ACS circuit 5, the pass metric of all passes capable of transition to the state is calculated and compared and the pass corresponding to the pass metric of maximum likelihood is selected.