公开(公告)号：US20240234157A9

公开(公告)日：2024-07-11

申请号：US17970899

申请日：2022-10-21

Applicant: Tokyo Electron Limited

Inventor： Alec Dorfner ,  Minjoon Park ,  Minseok Oh

IPC: H01L21/3065

CPC classification number: H01L21/30655

Abstract: A method of etching a target material using plasma includes cyclically performing the steps of an etch step for a first duration to etch a target material exposed in openings of a patterned mask material, and a flash step for a second duration after the first duration to remove polymer material accumulated at the openings during the etch step. The etch step is performed by generating plasma from an etch precursor gas including an etchant species. The target material may be a dielectric, such as a dielectric target material that includes an oxide. The flash step is performed by generating plasma from a flash precursor gas. Bias power may be provided to the substrate during the flash step. The flash species is different from the etchant species. The flash precursor gas may include oxygen and no fluorocarbons.

公开(公告)号：US20230397416A1

公开(公告)日：2023-12-07

申请号：US17831695

申请日：2022-06-03

Applicant: Tokyo Electron Limited

Inventor： Alec Dorfner ,  Minjoon Park

IPC: H01L27/11524 ,  H01L21/311 ,  H01L27/105 ,  H01L27/1157 ,  H01L27/06 ,  H01L27/108

CPC classification number: H01L27/11524 ,  H01L21/31144 ,  H01L27/1052 ,  H01L27/1157 ,  H01L27/0688 ,  H01L27/10802

Abstract: A method for forming a semiconductor device includes forming a first metal layer on top of an amorphous mask layer disposed over a substrate, forming a second metal layer that covers vertical sidewalls of openings in the amorphous mask layer, and etching a pattern in the substrate using the first metal layer and the second metal layer as an etch mask.

公开(公告)号：US20240249921A1

公开(公告)日：2024-07-25

申请号：US18156917

申请日：2023-01-19

Applicant: Tokyo Electron Limited

Inventor： Minjoon Park ,  Andrew Metz

IPC: H01J37/32 ,  H01L21/311

CPC classification number: H01J37/32477 ,  H01J37/32642 ,  H01J37/32743 ,  H01J37/32807 ,  H01L21/31116 ,  H01L21/31144 ,  H01J37/32091 ,  H01J37/3288 ,  H01J2237/201 ,  H01J2237/24585 ,  H01J2237/334

Abstract: A method of etching a substrate includes loading the substrate into a plasma etch chamber, the plasma etch chamber including a focus ring surrounding the substrate, the focus ring including a bulk material and a surface layer, the surface layer including a refractory metal; flowing a process gas including fluorine and carbon into the plasma etch chamber; coating a carbide layer over the surface layer of the focus ring, the coating including exposing the focus ring to a plasma generated from the process gas in the plasma etch chamber, the carbide layer including a carbide of the refractory metal; and etching the substrate, the etching including exposing the substrate to the plasma.

公开(公告)号：US12040176B2

公开(公告)日：2024-07-16

申请号：US17706408

申请日：2022-03-28

Applicant: Tokyo Electron Limited

Inventor： Shihsheng Chang ,  Andrew Metz ,  Yun Han ,  Minjoon Park ,  Ya-Ming Chen

IPC: H01L21/02 ,  H10B43/20

CPC classification number: H01L21/02115 ,  H01L21/02172 ,  H01L21/02488 ,  H01L21/02592 ,  H10B43/20

Abstract: A semiconductor device structure includes a dielectric layer formed on a silicon substrate, an amorphous carbon layer (ACL) formed on the dielectric layer, and a charge dissipation layer formed between the ACL and the dielectric layer. The charge dissipation layer is formed from a material having a resistivity lower than the resistivity of the ACL. Methodologies to fabricate the semiconductor device structure are also disclosed and include forming the dielectric layer on the silicon substrate, forming the charge dissipation layer on the dielectric layer, and forming the ACL on the charge dissipation layer. Alternative semiconductor device structures and fabrication methodologies are also disclosed.

公开(公告)号：US20230395385A1

公开(公告)日：2023-12-07

申请号：US17832897

申请日：2022-06-06

Applicant: Tokyo Electron Limited

Inventor： Minjoon Park ,  Andrew Metz

IPC: H01L21/3065 ,  H01L21/3213

CPC classification number: H01L21/3065 ,  H01L21/32136 ,  H01L21/32139

Abstract: A method of processing a substrate that includes: loading the substrate into a plasma etch chamber, the substrate including a patterned hard mask layer and an underlying layer, the plasma etch chamber including: a chamber part having a surface including a refractory metal; and a first electrode; flowing a process gas into the plasma etch chamber; while flowing the process gas, applying a source power to the first electrode of the plasma etch chamber to generate a plasma in the plasma etch chamber; exposing the surface of the chamber part to the plasma to sputter the refractory metal from the surface of the chamber part; and exposing the substrate to the plasma to deposit the refractory metal onto a portion of the patterned hard mask layer and etch the underlying layer selectively to the patterned hard mask layer.

公开(公告)号：US20240339328A1

公开(公告)日：2024-10-10

申请号：US18296503

申请日：2023-04-06

Applicant: Tokyo Electron Limited

Inventor： Alec Dorfner ,  Minjoon Park

IPC: H01L21/311 ,  H01L21/02 ,  H01L21/033 ,  H01L21/3105 ,  H01L21/768

CPC classification number: H01L21/31116 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/0332 ,  H01L21/31051 ,  H01L21/31144 ,  H01L21/76819 ,  H01L21/76834 ,  H01L21/76877 ,  H01L23/5283 ,  H01L23/53257 ,  H10B41/35 ,  H10B43/35

Abstract: A method of processing a substrate that includes: forming a conformal etch stop layer (ESL) over a staircase pattern of the substrate, the staircase pattern including staircases, each of the staircases including a conductive surface; forming a dielectric layer over the ESL; planarizing a top surface of the dielectric layer; forming a patterned hardmask over the dielectric layer; and etching the dielectric layer selectively to the ESL using the patterned hardmask as an etch mask to form a plurality of recesses, each of the plurality of recesses landing on each of the staircases, the ESL protecting the conductive surface from the etching, the etching including exposing the substrate to a plasma generated from a process gas including a fluorocarbon, O2, and WF6, a flow rate of WF6 being between 0.01% and 1% of a total gas flow rate of the process gas.

公开(公告)号：US20240222132A1

公开(公告)日：2024-07-04

申请号：US18090434

申请日：2022-12-28

Applicant: Tokyo Electron Limited

Inventor： Jinying Lin ,  Minjoon Park

IPC: H01L21/308

CPC classification number: H01L21/3086 ,  H01L21/3081

Abstract: Methods for the fabrication of semiconductor devices are disclosed. A method may include depositing a mask layer on a substrate, forming a protection layer on the mask layer, and modifying the protection layer such that a porosity of the protection layer is reduced. Modifying the protection layer may include densifying the protection layer. Modifying the protection layer may include reducing the protection layer using a hydrogen plasma. The method may include etching the protection layer and the substrate. Etching may include etching, forming the protection layer, and modifying the protection layer in a predetermined number of cycles.

公开(公告)号：US20240079246A1

公开(公告)日：2024-03-07

申请号：US17901727

申请日：2022-09-01

Applicant: Tokyo Electron Limited

Inventor： Alec Dorfner ,  Minjoon Park

IPC: H01L21/308

CPC classification number: H01L21/3086 ,  H01L21/3081

Abstract: A method for forming a semiconductor device is disclosed. The method includes forming a first metal layer on top of an amorphous mask layer disposed over a substrate. The method includes forming a second metal layer that extends along vertical sidewalls of an opening in the amorphous mask layer. The method includes forming a first recess partially extending into the substrate using the first metal layer and the second metal layer as a first etch mask. The method includes forming a third metal layer that extends along vertical sidewalls of the first recess. The method includes forming a second recess below the first recess using the first to third metal layers as a second etch mask.

公开(公告)号：US20250166966A1

公开(公告)日：2025-05-22

申请号：US18516562

申请日：2023-11-21

Applicant: Tokyo Electron Limited

Inventor： Pingshan Luan ,  Minjoon Park

IPC: H01J37/32

Abstract: A plasma processing method includes applying AC waveforms to a bottom electrode in a plasma chamber to generate a plasma. The method further includes applying a first pulse train including a first plurality of DC pulses to a top electrode in the plasma chamber, where each DC pulse of the first plurality of DC pulses includes a first on-state and a first off-state. And the method further includes applying a second pulse train including a second plurality of DC pulses to the bottom electrode in the plasma chamber, and where each DC pulse of the second plurality of DC pulses includes a second on-state and a second off-state, the first pulse train being offset in phase relative to the second pulse train so that each first off-state overlaps with each second on-state.

公开(公告)号：US20240249927A1

公开(公告)日：2024-07-25

申请号：US18156900

申请日：2023-01-19

Applicant: Tokyo Electron Limited

Inventor： Minjoon Park ,  Andrew Metz

IPC: H01J37/34 ,  H01J37/32 ,  H01L21/311

CPC classification number: H01J37/3473 ,  H01J37/32642 ,  H01J37/32743 ,  H01L21/31116 ,  H01L21/31144 ,  H01J37/32091 ,  H01J37/321 ,  H01J37/32568 ,  H01J2237/3341

Abstract: A method of etching a substrate that includes: loading the substrate into a plasma etch chamber, the substrate including a patterned hard mask layer and an underlying layer, the plasma etch chamber including a chamber part having a surface including a refractory metal, and a first electrode; flowing a process gas including fluorine and carbon into the plasma etch chamber; applying a source power to the first electrode of the plasma etch chamber to generate a plasma in the plasma etch chamber; and etching the underlying layer, the etching including exposing the surface of the chamber part to the plasma to sputter the refractory metal from the surface of the chamber part, and forming a recess in the underlying layer and a conductive polymer layer including the refractory metal over sidewalls of the patterned hard mask layer and the underlying layer, the forming including exposing the substrate to the plasma.