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    IC production with embedded DRAM circuits and logic circuits on single chip
    3.
    发明专利
    IC production with embedded DRAM circuits and logic circuits on single chip 未知

    公开(公告)号：NL1007804C2

    公开(公告)日：1999-06-17

    申请号：NL1007804

    申请日：1997-12-16

    Applicant: UNITED MICROELECTRONICS CORP

    Inventor： WU HONG-JEN ,  SUN SHIH-WEI ,  CHEN JACOB ,  YEW TRI-RUNG

    IPC: H01L21/8242 ,  H01L27/108 ,  H01L21/768

    Abstract: Production of an IC component, with embedded DRAM circuits and logic circuits on a single substrate, involves (a) producing transfer FETs (104) in and on embedded DRAM circuit regions of the substrate (100); (b) producing logic FETs (120) in and on the logic circuit regions of the substrate (100); (c) forming a first insulating layer (136) on the transfer FETs (104) and on the logic FET (120)s; (d) defining first and second openings (146, 148) in the first insulating layer to expose the source/drain regions (138, 140) of at least one of the transfer FETs (104) and defining a third opening (150) to expose at least one conductor (134) within the logic circuit; (e) producing a first conductive layer (152) on the first insulating layer and within the openings for contacting one of the source/drain regions of a transfer FET (104), the conductive layer not filling the first opening (146); (f) producing a capacitor dielectric layer and then a second conductive layer within the first opening (146); and (g) patterning the conductive layers for laterally delimiting the upper and lower electrodes of a charge storage capacitor of an embedded DRAM.

    Process for making an integrated circuit device with embedded DRAM
    5.
    发明专利
    Process for making an integrated circuit device with embedded DRAM 未知

    公开(公告)号：GB2331839A

    公开(公告)日：1999-06-02

    申请号：GB9725020

    申请日：1997-11-26

    Applicant: UNITED MICROELECTRONICS CORP

    Inventor： WU H J ,  SUN SHIH-WEI ,  CHEN JACOB ,  YEW TRI-RUNG

    IPC: H01L21/8242 ,  H01L27/108

    Abstract: Transfer FETs 104 and wiring lines 106 are provided for the embedded DRAM circuits and FETs 120 are provided for the logic portions of the device in an initial phase of the process. The gate electrodes and source/drain regions 142,144 of the logic FETs may be subjected to a salicide process at this initial phase and a thick planarized oxide layer 136 is provided over both the embedded DRAM regions and the logic circuit regions. Capacitors and logic interconnects are next formed, preferably using common etching, titanium nitride deposition and tungsten deposition steps. Contact vias 146,148,150 are formed to expose each of the source/drain regions 138,140 of the DRAM transfer FETs and to expose select conductors within the logic circuits. A conductor layer 152 e.g. of titanium nitride is deposited over the device and within the various contact vias through the planarized oxide layer 136. A capacitor dielectric layer 154 e.g. of tantalum pentoxide is provided over the device and then the capacitor dielectric layer is selectively removed from the contact vias 148,150 that become bit line contacts and logic interconnects. A conductive layer e.g. of tungsten is deposited and patterned to provide upper capacitor electrodes 158 and to complete the bit line contacts 160 and logic interconnects 162. The tungsten layer also can provide bit line wiring. The ¢ V cc potential for the upper capacitor electrodes can be provided to the circuit using a level of interconnect wiring 180,182 also used by the logic circuits.

    IC production with embedded DRAM circuits and logic circuits on single chip
    6.
    发明专利
    IC production with embedded DRAM circuits and logic circuits on single chip 未知

    公开(公告)号：DE19757490A1

    公开(公告)日：1999-01-28

    申请号：DE19757490

    申请日：1997-12-23

    Applicant: UNITED MICROELECTRONICS CORP

    Inventor： WU H J ,  SUN SHIH-WEI ,  CHEN JACOB ,  YEW TRI-RUNG

    IPC: H01L21/8242 ,  H01L27/108

    Abstract: Production of an IC component, with embedded DRAM circuits and logic circuits on a single substrate, involves (a) producing transfer FETs (104) in and on embedded DRAM circuit regions of the substrate (100); (b) producing logic FETs (120) in and on the logic circuit regions of the substrate (100); (c) forming a first insulating layer (136) on the transfer FETs (104) and on the logic FET (120)s; (d) defining first and second openings (146, 148) in the first insulating layer to expose the source/drain regions (138, 140) of at least one of the transfer FETs (104) and defining a third opening (150) to expose at least one conductor (134) within the logic circuit; (e) producing a first conductive layer (152) on the first insulating layer and within the openings for contacting one of the source/drain regions of a transfer FET (104), the conductive layer not filling the first opening (146); (f) producing a capacitor dielectric layer and then a second conductive layer within the first opening (146); and (g) patterning the conductive layers for laterally delimiting the upper and lower electrodes of a charge storage capacitor of an embedded DRAM.

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