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    Dual damascene process for integrated circuits
    5.
    发明专利
    Dual damascene process for integrated circuits 未知

    公开(公告)号：FR2763424A1

    公开(公告)日：1998-11-20

    申请号：FR9705992

    申请日：1997-05-15

    Applicant: UNITED MICROELECTRONICS CORP

    Inventor： YEW TRI RUNG ,  LIU MONG CHUNG ,  LUR WATER ,  SUN SHIH WEI

    IPC: H01L21/28 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/522

    Abstract: Making an integrated circuit with first (78) and second (76) level conductor structures comprises: (a) providing a substrate (50) with integrated circuit device(s); (b) providing an interlayer dielectric layer (52) over the substrate; (c) providing an etch stop layer (54) over it; (d) patterning the etch stop layer to define openings corresponding to positions where first level conductor structures are to be formed; (e) providing an intermetallic dielectric layer (58) over the patterned etch stop layer; (f) forming a second level mask over the intermetallic dielectric layer; this mask having openings corresponding to positions where second level conductor structures are to be formed; (g) etching through the openings in the second level mask to form second level conductor openings in the intermetallic dielectric layer; (h) etching through the openings in the patterned etch stop layer to form first level conductor openings in the interlayer dielectric layer; the edges of the openings have a tapered configuration; they provide for a step-free transition with the second level conductor openings; and (i) depositing metal into the first and second level conductor openings.

    Poly:silicon CMP processing high density DRAM memory cell structure
    6.
    发明专利
    Poly:silicon CMP processing high density DRAM memory cell structure 未知

    公开(公告)号：FR2761198A1

    公开(公告)日：1998-09-25

    申请号：FR9703423

    申请日：1997-03-20

    Applicant: UNITED MICROELECTRONICS CORP

    Inventor： SUN SHIH WEI

    IPC: H01L27/04 ,  H01L21/02 ,  H01L21/321 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/108

    Abstract: Producing memory device on substrate, which has a charge storage capacitor, includes the following: - Provide a transistor, which has already formed source/drain and gate electrode on its surface; - Deposit 1st insulating layer on transistor; - Deposit 2nd insulating layer, which has different material with 1st insulating, on 1st insulating layer; - Through 1st and 2nd insulating layer to provide 1st contact window to expose 1st source/drain of transistor; - Deposit 1st polysilicon on 2nd insulating layer, the 1st polysilicon is doing electrical contact with 1st source/drain of transistor; - Deposit 3rd insulating layer on 1st polysilicon layer, and image 3rd insulating layer to provide 2nd contact window to expose 1st polysilicon layer; - Deposit 2nd polysilicon to fill 2nd contact window; - Proceed polishing to remove redundant part of 2nd polysilicon; - Remove 3rd insulating layer to expose polysilicon superstructure vertically extended on 1st polysilicon layer, and form portion of bottom electrode of charge storage capacitor; - Form dielectric on top of polysilicon superstructure and 1st polysilicon layer; - Deposit 3rd polysilicon layer, and form upper electrode of charge storage capacitor.

    High capacitance charge storage capacitor for a DRAM
    8.
    发明专利
    High capacitance charge storage capacitor for a DRAM 未知

    公开(公告)号：FR2770930A1

    公开(公告)日：1999-05-14

    申请号：FR9714035

    申请日：1997-11-07

    Applicant: UNITED MICROELECTRONICS CORP

    Inventor： YEW TRI RUNG ,  LUR WATER ,  SUN SHIH WEI

    IPC: H01L21/02 ,  H01L21/8242 ,  H01L27/108

    Abstract: A method of providing increased capacitance to a charge storage structure in an integrated circuit comprises providing an access circuit, in and on a substrate, which controls access to an electrode of the structure through an electrode contact. A first conductive layer is provided over the substrate and connected to the electrode contact, and a layer of dielectric material is provided over the conductive layer. A layer of grains of polysilicon is provided over the layer of dielectric material so as to leave uncovered portions between the grains, which are selectively removed to form spaced apart columns of dielectric material extending above the first conductive layer. A conformal second conductive layer is provided over the columns followed by a capacitor dielectric layer and a third conductive layer.

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