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    METHOD OF FORMING LOCAL INTERCONNECTION
    1.
    发明专利
    METHOD OF FORMING LOCAL INTERCONNECTION 失效

    公开(公告)号：JP2000021886A

    公开(公告)日：2000-01-21

    申请号：JP30432898

    申请日：1998-10-26

    Applicant: UNITED MICROELECTRONICS CORP

    Inventor： LIOU FU-TAI

    IPC: H01L21/3205 ,  H01L21/28 ,  H01L21/768

    Abstract: PROBLEM TO BE SOLVED: To simply make local interconnections by forming a heat-resistive metal oxide layer on a substrate, treating any part thereof with H to convert to a semiconductor or conductor acting as local interconnections. SOLUTION: A semiconductor substrate 100 has e.g. an MOS device 101 and electrolytic oxide layer 102 (if having a plurality of devices, the devices are insulated), e.g. heat-resistive metal oxide layer 103 composed of a TiO2 layer, Ta2O5 layer, Fe2O3 layer, BaTiO3 layer or combined layer thereof is formed on the entire surface of the substrate 100 and partly covered with a mask layer 104, and the H plasma or H heat treatment is applied to the part 103b covered with the mask layer 104 and exposed part 103a with the mask layer 104 used as a mask or diffusion barrier layer. This improves the conductivity of the exposed part 103a of the heat-resistive metal oxide layer 103 and converts the insulator to a semiconductor or conductor.

    MANUFACTURE OF RESISTOR FOR INTEGRATED CIRCUIT
    2.
    发明专利
    MANUFACTURE OF RESISTOR FOR INTEGRATED CIRCUIT 失效

    公开(公告)号：JP2000031389A

    公开(公告)日：2000-01-28

    申请号：JP30432998

    申请日：1998-10-26

    Applicant: UNITED MICROELECTRONICS CORP

    Inventor： LIOU FU-TAI

    IPC: H01L27/04 ,  C22B5/12 ,  H01L21/02 ,  H01L21/822 ,  H01L27/08

    Abstract: PROBLEM TO BE SOLVED: To form a resistor in an integrated circuit without using a polysilicon, by converting a selected part of a heat-resistant metal oxide layer into a conductive oxide of a specific resistance characteristics which acts as a desired resistor. SOLUTION: Firstly, a heat-resistant metal oxide layer 101 is formed on a substrate 100. Then, a mask layer 102 such as a photo-resist layer or a diffusion barrier layer is formed on the heat-resistant metal oxide layer 101. The mask layer 102 is selectively removed to form a contact hole 103 at the mask layer 102, so that the selected part 101a of the heat-resistant metal oxide layer 101 is exposed. Then a wafer 100 is oxygen-plasma processed or oxygen-thermal processed through the mask layer 102 so that the part 101a which is not masked is converted to a conductive oxide of a specific resistance characteristics. When the entire mask layer 102 is removed, the conductive oxide 101a of the heat- resistant metal oxide 101 functions as a desired resistor.

    MANUFACTURE OF EMBEDDED DYNAMIC RANDOM ACCESS MEMORY
    3.
    发明专利
    MANUFACTURE OF EMBEDDED DYNAMIC RANDOM ACCESS MEMORY 失效

    公开(公告)号：JP2000036572A

    公开(公告)日：2000-02-02

    申请号：JP30433098

    申请日：1998-10-26

    Applicant: UNITED MICROELECTRONICS CORP

    Inventor： LIOU FU-TAI ,  RO KATETSU

    IPC: H01L27/108 ,  H01L21/8242

    Abstract: PROBLEM TO BE SOLVED: To improve the flatness of an integrated circuit by hydrogen-treating a heat resistant metal oxide deposited by using a hydrogen plasma or hot hydrogen, and altering non-electric conductivity of the treated metal oxide to electric conductivity. SOLUTION: A heat resistant metal oxide layer hydrogen-treated by using a hydrogen plasma or hot hydrogen and exposed is converted into a conductive layer. Heat resistant metal oxide layers 116b1 116b2 exposed by the hydrogen- treatment are converted into conductive layers. Meanwhile, non-exposed heat resistant metal oxide layer 116a is still retained in a state of a non-conductive layer. A second conductive layer is formed on the metal oxide layer, and then patterned. As a result an upper surface of an upper electrode 118a of a capacitor 120 and first and second contact mutual connectors 121, 122 become the same relative heights. Thus, the smoothness (flatness) of the integrated circuit can be improved.

    FABRICATION OF LOAD RESISTOR
    4.
    发明专利
    FABRICATION OF LOAD RESISTOR 失效

    公开(公告)号：JP2000150671A

    公开(公告)日：2000-05-30

    申请号：JP32109098

    申请日：1998-11-11

    Applicant: UNITED MICROELECTRONICS CORP

    Inventor： LIOU FU-TAI

    IPC: H01C7/00 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8244 ,  H01L27/04 ,  H01L27/11

    Abstract: PROBLEM TO BE SOLVED: To fabricate a load resistor having a sufficiently high resistance by performing hydrogen treatment twice and converting a heat resistant metal oxide layer into a low resistance conductive layer, a high resistance conductive layer and an insulating layer. SOLUTION: A first mask is formed partially on a heat resistant metal oxide layer and the exposed part thereof is subjected to first time hydrogen treatment. The part subjected to hydrogen treatment is converted from an insulator to high resistance conductors 9a, 9b. Subsequently, a second mask is formed partially on the heat resistant metal oxide layer and the exposed part thereof is subjected to second time hydrogen treatment. The treated part is converted into low resistance conductors 9c, 9d, 9e, 9f, 9g, 9h. The part covered with the second mask is left as insulators 9i, 9j, 9k. Consequently, load resistors 9a, 9b and interconnections 9c-9h are formed.

    6.
    发明专利
    未知

    公开(公告)号：NL1010429C2

    公开(公告)日：2000-05-03

    申请号：NL1010429

    申请日：1998-10-29

    Applicant: UNITED MICROELECTRONICS CORP

    Inventor： LIOU FU-TAI

    IPC: H01L27/108 ,  H01L21/8242 ,  H01L21/441

    Abstract: A method of manufacturing embedded DRAM capable of integrating memory circuit regions and logic circuit regions together such that their top surfaces are at the same height, and hence able to maintain a high degree of planarity in integrated circuits. The method includes depositing a layer of refractory metal oxide over a high aspect ratio contact hole. Then, through the selective application of a hydrogen plasma treatment or hot hydrogen treatment, a portion of the deposited refractory metal oxide on the contact hole is transformed from non-conductive to conductive material, whereas the refractory metal oxide without a hydrogen plasma treatment or hot hydrogen treatment remains non-conductive. Therefore, a non-conductive refractory metal oxide layer can be used as a dielectric layer for a DRAM capacitor.

    7.
    发明专利
    未知

    公开(公告)号：NL1010614C2

    公开(公告)日：2000-05-23

    申请号：NL1010614

    申请日：1998-11-20

    Applicant: UNITED MICROELECTRONICS CORP

    Inventor： LIOU FU-TAI

    IPC: H01L21/02 ,  H01L21/822 ,  H01L21/8244 ,  H01C7/00 ,  H01L27/04 ,  H01L27/11

    Abstract: A method of fabricating a load resistor. The load resistor is often applied in a static random access memory. The interconnect between different conductive regions such as gate and source/drain region is formed by applying a hydrogen treatment to a refractory metal oxide layer, while the load resistors are formed by applying a hydrogen treatment with different parameters as the former one. The insulation is formed by the refractory metal oxide layer which is not to be covered.

    Embedded DRAM, used in a microprocessor or digital signal processor
    8.
    发明专利
    Embedded DRAM, used in a microprocessor or digital signal processor 未知

    公开(公告)号：DE19849743A1

    公开(公告)日：2000-01-13

    申请号：DE19849743

    申请日：1998-10-28

    Applicant: UNITED MICROELECTRONICS CORP

    Inventor： LIOU FU-TAI ,  LUR WATER

    IPC: H01L27/108 ,  H01L21/8242

    Abstract: An embedded DRAM production process comprises selective hydrogen treatment of a high melting metal oxide layer to form a conductive portion for a contact connection and leave a dielectric portion for a DRAM capacitor. An embedded DRAM production process comprises: (a) providing a substrate having a memory circuit region with transfer FETs and a logic circuit region with logic FETs; (b) applying and structuring a first insulating layer to form first and second source/drain region exposure openings above the memory circuit region and third conductive region exposure openings above the logic circuit region; (c) applying a first conductive layer which does not completely fill the openings; (d) applying a high melting metal oxide layer; (e) applying a masking layer which covers the first openings but not the second and third openings; (f) treating with hydrogen to convert the exposed metal oxide into electrically conductive material; (g) removing the mask; and (h) applying and structuring a second conductive layer such that a first electrode, a dielectric layer and a lower electrode are formed above each first opening and contact connections are formed above the second and third openings. Preferred Features: The high melting metal oxide is TiO2, Ta2O5, Fe2O3 or BaTiO3.

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