公开(公告)号：EP2555240B1

公开(公告)日：2020-04-15

申请号：EP12179424.2

申请日：2012-08-06

Applicant: Unimicron Technology Corp. ,  Industrial Technology Research Institute

Inventor： Hu, Dyi-Chung ,  Lau, John Hon-Shing

IPC: H01L23/14 ,  H01L23/498 ,  H01L23/13

公开(公告)号：EP2560201B1

公开(公告)日：2019-10-02

申请号：EP11194105.0

申请日：2011-12-16

Applicant: Unimicron Technology Corp.

Inventor： Hu, Dyi-Chung ,  Hu, Yu-Shan

IPC: H01L23/36 ,  H01L23/367 ,  H01L23/538

公开(公告)号：EP2560201A3

公开(公告)日：2014-07-02

申请号：EP11194105.0

申请日：2011-12-16

Applicant: Unimicron Technology Corp.

Inventor： Hu, Dyi-Chung ,  Hu, Yu-Shan

IPC: H01L23/36 ,  H01L23/367 ,  H01L23/538

CPC classification number: H01L23/5389 ,  H01L23/36 ,  H01L23/3677 ,  H01L24/97 ,  H01L2224/45144 ,  H01L2224/4824 ,  H01L2924/01029 ,  H01L2924/12042 ,  H01L2924/00015 ,  H01L2924/00

Abstract: A semiconductor packaging structure includes a semiconductor chip, a packaging layer, a dielectric layer, a wiring layer, and a metallic foil. The semiconductor chip has an active surface, an inactive surface opposing the active surface, electrode pads formed on the active surface, and metal bumps formed on the electrode pads. The packaging layer encapsulates the semiconductor chip and exposes the active surface. The dielectric layer is formed on the active surface and a surface of the packaging layer at the same side with the active surface, and has wiring pattern openings for the metal bumps to be exposed therefrom. The wiring layer is formed in the wiring pattern openings. The metallic foil is disposed on the packaging layer adjacent to the inactive surface. Metallic protrusions are formed on the metallic foil, and penetrate the packaging layer to extend to the inactive surface of the semiconductor chip.

公开(公告)号：EP2560201A2

公开(公告)日：2013-02-20

申请号：EP11194105.0

申请日：2011-12-16

Applicant: Unimicron Technology Corp.

Inventor： Hu, Dyi-Chung ,  Hu, Yu-Shan

IPC: H01L23/36 ,  H01L23/367 ,  H01L23/538

CPC classification number: H01L23/5389 ,  H01L23/36 ,  H01L23/3677 ,  H01L24/97 ,  H01L2224/45144 ,  H01L2224/4824 ,  H01L2924/01029 ,  H01L2924/12042 ,  H01L2924/00015 ,  H01L2924/00

Abstract: A semiconductor packaging structure includes a semiconductor chip, a packaging layer, a dielectric layer, a wiring layer, and a metallic foil. The semiconductor chip has an active surface, an inactive surface opposing the active surface, electrode pads formed on the active surface, and metal bumps formed on the electrode pads. The packaging layer encapsulates the semiconductor chip and exposes the active surface. The dielectric layer is formed on the active surface and a surface of the packaging layer at the same side with the active surface, and has wiring pattern openings for the metal bumps to be exposed therefrom. The wiring layer is formed in the wiring pattern openings. The metallic foil is disposed on the packaging layer adjacent to the inactive surface. Metallic protrusions are formed on the metallic foil, and penetrate the packaging layer to extend to the inactive surface of the semiconductor chip.

Abstract translation: 半导体封装结构包括半导体芯片，封装层，电介质层，布线层和金属箔。 半导体芯片具有活性表面，与活性表面相对的非活性表面，形成在活性表面上的电极焊盘以及形成在电极焊盘上的金属凸块。 包装层封装半导体芯片并暴露活性表面。 电介质层在活性表面和与活性表面相同侧的包装层的表面上形成，并且具有用于金属凸块暴露的布线图案孔。 布线层形成在布线图形开口中。 金属箔设置在与非活性表面相邻的包装层上。 在金属箔上形成金属突起，穿透包装层延伸到半导体芯片的非活性表面。

公开(公告)号：EP2555240A1

公开(公告)日：2013-02-06

申请号：EP12179424.2

申请日：2012-08-06

Applicant: Unimicron Technology Corp. ,  Industrial Technology Research Institute

Inventor： Hu, Dyi-Chung ,  Lau, John Hon-Shing

IPC: H01L25/065 ,  H01L23/14 ,  H01L23/498

Abstract: A packaging substrate includes a carrier and an interposer. The carrier has opposite top and bottom surfaces. A recess is disposed in the top surface and a plurality of first conductive terminals are disposed on the bottom of the recess. Further, a plurality of second conductive terminals are disposed on the bottom surface of the carrier. The interposer is disposed in the recess and has opposite first and second surfaces and a plurality of conductive through vias penetrating the first and second surfaces. A first conductive pad is disposed on an end of each of the conductive through vias exposed from the first surface, and a second conductive pad is disposed on the other end of the conductive through via exposed from the second surface and electrically connected to a corresponding one of the first conductive terminals. Compared with the prior art, the invention improves the product reliability.

Abstract translation: 甲封装基板包括载体和在中介层上。 该载体具有相对的顶部和底部表面。 的凹部在其顶表面设置，并且第一导电端子的多元化是在凹部的底部处。 此外，第二导电端子的多元被设置在载体的下表面上。 该内插器是在所述凹部设置，并且具有相对的第一和第二表面和通孔穿透第一和第二表面的导电复数。 第一导电垫被设置在每个导电的端部通过从所述第一表面暴露的通孔设置在和第二导电板经由通孔从所述第二表面暴露的并且电连接到相应的一个设置在导电的另一端 的第一导电端子。 与现有技术相比，本发明提高了产品的可靠性。