公开(公告)号：EP2560201B1

公开(公告)日：2019-10-02

申请号：EP11194105.0

申请日：2011-12-16

Applicant: Unimicron Technology Corp.

Inventor： Hu, Dyi-Chung ,  Hu, Yu-Shan

IPC: H01L23/36 ,  H01L23/367 ,  H01L23/538

公开(公告)号：EP2560201A3

公开(公告)日：2014-07-02

申请号：EP11194105.0

申请日：2011-12-16

Applicant: Unimicron Technology Corp.

Inventor： Hu, Dyi-Chung ,  Hu, Yu-Shan

IPC: H01L23/36 ,  H01L23/367 ,  H01L23/538

CPC classification number: H01L23/5389 ,  H01L23/36 ,  H01L23/3677 ,  H01L24/97 ,  H01L2224/45144 ,  H01L2224/4824 ,  H01L2924/01029 ,  H01L2924/12042 ,  H01L2924/00015 ,  H01L2924/00

Abstract: A semiconductor packaging structure includes a semiconductor chip, a packaging layer, a dielectric layer, a wiring layer, and a metallic foil. The semiconductor chip has an active surface, an inactive surface opposing the active surface, electrode pads formed on the active surface, and metal bumps formed on the electrode pads. The packaging layer encapsulates the semiconductor chip and exposes the active surface. The dielectric layer is formed on the active surface and a surface of the packaging layer at the same side with the active surface, and has wiring pattern openings for the metal bumps to be exposed therefrom. The wiring layer is formed in the wiring pattern openings. The metallic foil is disposed on the packaging layer adjacent to the inactive surface. Metallic protrusions are formed on the metallic foil, and penetrate the packaging layer to extend to the inactive surface of the semiconductor chip.

公开(公告)号：EP2560201A2

公开(公告)日：2013-02-20

申请号：EP11194105.0

申请日：2011-12-16

Applicant: Unimicron Technology Corp.

Inventor： Hu, Dyi-Chung ,  Hu, Yu-Shan

IPC: H01L23/36 ,  H01L23/367 ,  H01L23/538

CPC classification number: H01L23/5389 ,  H01L23/36 ,  H01L23/3677 ,  H01L24/97 ,  H01L2224/45144 ,  H01L2224/4824 ,  H01L2924/01029 ,  H01L2924/12042 ,  H01L2924/00015 ,  H01L2924/00

Abstract: A semiconductor packaging structure includes a semiconductor chip, a packaging layer, a dielectric layer, a wiring layer, and a metallic foil. The semiconductor chip has an active surface, an inactive surface opposing the active surface, electrode pads formed on the active surface, and metal bumps formed on the electrode pads. The packaging layer encapsulates the semiconductor chip and exposes the active surface. The dielectric layer is formed on the active surface and a surface of the packaging layer at the same side with the active surface, and has wiring pattern openings for the metal bumps to be exposed therefrom. The wiring layer is formed in the wiring pattern openings. The metallic foil is disposed on the packaging layer adjacent to the inactive surface. Metallic protrusions are formed on the metallic foil, and penetrate the packaging layer to extend to the inactive surface of the semiconductor chip.

Abstract translation: 半导体封装结构包括半导体芯片，封装层，电介质层，布线层和金属箔。 半导体芯片具有活性表面，与活性表面相对的非活性表面，形成在活性表面上的电极焊盘以及形成在电极焊盘上的金属凸块。 包装层封装半导体芯片并暴露活性表面。 电介质层在活性表面和与活性表面相同侧的包装层的表面上形成，并且具有用于金属凸块暴露的布线图案孔。 布线层形成在布线图形开口中。 金属箔设置在与非活性表面相邻的包装层上。 在金属箔上形成金属突起，穿透包装层延伸到半导体芯片的非活性表面。