公开(公告)号：US12218017B2

公开(公告)日：2025-02-04

申请号：US17586106

申请日：2022-01-27

Applicant: UNIMICRON TECHNOLOGY CORP.

Inventor： Wen Yu Lin ,  Kai-Ming Yang ,  Pu-Ju Lin

IPC: C03C17/00 ,  C03C17/22 ,  C03C17/42 ,  H01L23/10 ,  H01L23/15 ,  H01L23/29 ,  H05K1/03

Abstract: The invention discloses a glass carrier having a protection structure, comprising a glass body and a protection layer. The glass body has a top surface, a bottom surface, and a lateral surface. The protection layer covers the lateral surface of the glass body. The protection layer is a hard material with a stiffness coefficient higher than a stiffness coefficient of the glass body. The invention further discloses a manufacturing method of a glass carrier having a protection structure, comprising the following steps: covering the protection layer around the lateral surface of the glass body, wherein the protection layer is the hard material with the stiffness coefficient higher than the stiffness coefficient of the glass body.

公开(公告)号：US11637047B2

公开(公告)日：2023-04-25

申请号：US17875443

申请日：2022-07-28

Applicant: Unimicron Technology Corp.

Inventor： Pu-Ju Lin ,  Kai-Ming Yang ,  Cheng-Ta Ko

IPC: H01L21/56 ,  H01L23/31 ,  H01L23/522 ,  H01L23/00 ,  H01L21/78

Abstract: A manufacturing method of a chip package structure includes the following steps. A plurality of chips is disposed on a first insulating layer. The back surface of each of the chips is in direct contact with the first insulating layer. A stress buffer layer is formed to extend and cover the active surface and the peripheral surface of each of the chips, and a bottom surface of the stress buffer layer is aligned with the back surface of each of the chips. The stress buffer layer has an opening exposing a part of the active surface of each of the chips, and the redistribution layer is electrically connected to each of the chips through the opening. A plurality of solder balls is electrically connected to the redistribution layer exposed by the blind holes. A singularizing process is performed to form a plurality of chip package structures separated from each other.

公开(公告)号：US20220344248A1

公开(公告)日：2022-10-27

申请号：US17235944

申请日：2021-04-21

Applicant: Unimicron Technology Corp.

Inventor： John Hon-Shing Lau ,  Cheng-Ta Ko ,  Pu-Ju Lin ,  Kai-Ming Yang ,  Chi-Hai Kuo ,  Chia-Yu Peng ,  Tzyy-Jang Tseng

IPC: H01L23/498 ,  H01L25/065 ,  H01L23/538 ,  H01L23/00 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56

Abstract: A package structure includes a redistribution layer, a chip assembly, a plurality of solder balls, and a molding compound. The redistribution layer includes redistribution circuits, photoimageable dielectric layers, conductive through holes, and chip pads. One of the photoimageable dielectric layers located on opposite two outermost sides has an upper surface and openings. The chip pads are located on the upper surface and are electrically connected to the redistribution circuits through the conductive through holes. The openings expose portions of the redistribution circuits to define solder ball pads. Line widths and line spacings of the redistribution circuits decrease in a direction from the solder ball pads towards the chip pads. The chip assembly is disposed on the chip pads and includes at least two chips with different sizes. The solder balls are disposed on the solder ball pads, and the molding compound at least covers the chip assembly.

公开(公告)号：US11424216B2

公开(公告)日：2022-08-23

申请号：US17030380

申请日：2020-09-24

Applicant: Unimicron Technology Corp.

Inventor： Chia-Fu Hsu ,  Kai-Ming Yang ,  Pu-Ju Lin ,  Cheng-Ta Ko

IPC: H01L23/48 ,  H01L23/00

Abstract: A fabrication method of an electronic device bonding structure includes the following steps. A first electronic component including a first conductive bonding portion is provided. A second electronic component including a second conductive bonding portion is provided. A first organic polymer layer is formed on the first conductive bonding portion. A second organic polymer layer is formed on the second conductive bonding portion. Bonding is performed on the first electronic component and the second electronic component through the first conductive bonding portion and the second conductive bonding portion, such that the first electronic component and the second electronic component are electrically connected. The first organic polymer layer and the second organic polymer layer diffuse into the first conductive bonding portion and the second conductive bonding portion after the bonding. An electronic device bonding structure is also provided.

公开(公告)号：US11410933B2

公开(公告)日：2022-08-09

申请号：US17314055

申请日：2021-05-07

Applicant: Unimicron Technology Corp.

Inventor： John Hon-Shing Lau ,  Cheng-Ta Ko ,  Pu-Ju Lin ,  Tzyy-Jang Tseng ,  Ra-Min Tain ,  Kai-Ming Yang

IPC: H01L21/00 ,  H01L23/538 ,  H01L25/065 ,  H01L23/00 ,  H01L21/48 ,  H01L25/00

Abstract: A package structure, including a bridge, an interposer, a first redistribution structure layer, a second redistribution structure layer, and multiple chips, is provided. The bridge includes a silicon substrate, a redistribution layer, and multiple bridge pads. The interposer includes an intermediate layer, multiple conductive vias, multiple first pads, and multiple second pads. The bridge is embedded in the intermediate layer. The bridge pads are aligned with the upper surface. The first redistribution structure layer is disposed on the upper surface of the interposer and is electrically connected to the first pads and the bridge pads. The second redistribution structure layer is disposed on the lower surface of the interposer and is electrically connected to the second pads. The chips are disposed on the first redistribution structure layer and are electrically connected to the first redistribution structure layer. The chips are electrically connected to each other through the bridge.

公开(公告)号：US20200043839A1

公开(公告)日：2020-02-06

申请号：US16167540

申请日：2018-10-23

Applicant: Unimicron Technology Corp.

Inventor： Cheng-Ta Ko ,  Kai-Ming Yang ,  Yu-Hua Chen ,  Tzyy-Jang Tseng

IPC: H01L23/498

Abstract: A package substrate structure includes a first substrate, a second substrate, a plurality of conductive pillars and an adhesive layer. The first substrate includes a plurality of vias and a plurality of pads. The vias and the pads are disposed on the first substrate, and fills in the vias. The second substrate is disposed opposite to the first substrate. Each conductive pillar is disposed between the first substrate and the second substrate, where each conductive pillar electrically connects each pad and the second substrate, and the adhesive layer fills in the gaps between the conductive pillars. A bonding method of the package substrate structure is also provided.

公开(公告)号：US11710690B2

公开(公告)日：2023-07-25

申请号：US17233551

申请日：2021-04-19

Applicant: Unimicron Technology Corp.

Inventor： John Hon-Shing Lau ,  Cheng-Ta Ko ,  Pu-Ju Lin ,  Kai-Ming Yang ,  Chia-Yu Peng ,  Chi-Hai Kuo ,  Tzyy-Jang Tseng

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00

CPC classification number: H01L23/49816 ,  H01L21/486 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/13147 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/16238

Abstract: A package structure includes at least one first redistribution layer, at least one second redistribution layer, a chip pad, a solder ball pad, a chip, a solder ball, and a molding compound. The first redistribution layer includes a first dielectric layer and a first redistribution circuit that fills a first opening and a second opening of the first dielectric layer. The first dielectric layer is aligned with the first redistribution circuit. The second redistribution layer includes a second and a third dielectric layers and a second redistribution circuit. The third dielectric layer is aligned with the second redistribution circuit. The chip pad and the solder ball pad are electrically connected to the first and the second redistribution circuits respectively. The chip and the solder ball are disposed on the chip pad and the solder ball pad respectively. The molding compound at least covers the chip and the chip pad.

公开(公告)号：US11682612B2

公开(公告)日：2023-06-20

申请号：US17235944

申请日：2021-04-21

Applicant: Unimicron Technology Corp.

Inventor： John Hon-Shing Lau ,  Cheng-Ta Ko ,  Pu-Ju Lin ,  Kai-Ming Yang ,  Chi-Hai Kuo ,  Chia-Yu Peng ,  Tzyy-Jang Tseng

IPC: H01L23/538 ,  H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L25/065

CPC classification number: H01L23/49816 ,  H01L21/486 ,  H01L21/4857 ,  H01L21/565 ,  H01L23/3135 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/13 ,  H01L24/16 ,  H01L24/73 ,  H01L25/0655 ,  H01L2224/13147 ,  H01L2224/13582 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/73204 ,  H01L2924/1434 ,  H01L2924/14335 ,  H01L2924/35

Abstract: A package structure includes a redistribution layer, a chip assembly, a plurality of solder balls, and a molding compound. The redistribution layer includes redistribution circuits, photoimageable dielectric layers, conductive through holes, and chip pads. One of the photoimageable dielectric layers located on opposite two outermost sides has an upper surface and openings. The chip pads are located on the upper surface and are electrically connected to the redistribution circuits through the conductive through holes. The openings expose portions of the redistribution circuits to define solder ball pads. Line widths and line spacings of the redistribution circuits decrease in a direction from the solder ball pads towards the chip pads. The chip assembly is disposed on the chip pads and includes at least two chips with different sizes. The solder balls are disposed on the solder ball pads, and the molding compound at least covers the chip assembly.

公开(公告)号：US11516910B1

公开(公告)日：2022-11-29

申请号：US17371114

申请日：2021-07-09

Applicant: Unimicron Technology Corp.

Inventor： Chia-Yu Peng ,  John Hon-Shing Lau ,  Kai-Ming Yang ,  Pu-Ju Lin ,  Cheng-Ta Ko ,  Tzyy-Jang Tseng

IPC: H01R12/52 ,  H05K1/02 ,  H05K1/11 ,  H05K3/24 ,  H05K3/06 ,  H05K3/40

Abstract: A circuit board structure includes a redistribution structure layer, a build-up circuit structure layer, and a connection structure layer. The redistribution structure layer has a first and second surface, and includes an inner and outer dielectric layer, first connecting pads, and chip pads. A bottom surface of each first connecting pad is aligned with the first surface, and the chip pads are protruded from and located on the second surface. The build-up circuit structure layer includes second connecting pads. The connection structure layer is disposed between the redistribution structure layer and the build-up circuit structure layer and includes a substrate and conductive paste pillars penetrating the substrate. The first connecting pads are electrically connected to the second connecting pads via the conductive paste pillars, respectively. A top surface of each conductive paste pillar is aligned with the first surface of the redistribution structure layer.

公开(公告)号：US20220367307A1

公开(公告)日：2022-11-17

申请号：US17875443

申请日：2022-07-28

Applicant: Unimicron Technology Corp.

Inventor： Pu-Ju Lin ,  Kai-Ming Yang ,  Cheng-Ta Ko

IPC: H01L23/31 ,  H01L23/522 ,  H01L23/00 ,  H01L21/56 ,  H01L21/78

Abstract: A manufacturing method of a chip package structure includes the following steps. A plurality of chips is disposed on a first insulating layer. The back surface of each of the chips is in direct contact with the first insulating layer. A stress buffer layer is formed to extend and cover the active surface and the peripheral surface of each of the chips, and a bottom surface of the stress buffer layer is aligned with the back surface of each of the chips. The stress buffer layer has an opening exposing a part of the active surface of each of the chips, and the redistribution layer is electrically connected to each of the chips through the opening. A plurality of solder balls is electrically connected to the redistribution layer exposed by the blind holes. A singularizing process is performed to form a plurality of chip package structures separated from each other.