6.
    发明专利
    未知

    公开(公告)号:DE60035665T2

    公开(公告)日:2008-05-21

    申请号:DE60035665

    申请日:2000-12-13

    Applicant: XEROX CORP

    Abstract: A method and apparatus for reducing vertical leakage current in a high fill factor sensor array is described. Reduction of vertical leakage current is achieved by eliminating Schottky junction interfaces that occur between metal back contacts (46) and intrinsic amorphous silicon layers (50). One method of eliminating the Schottky junction uses an extra wide region of N doped amorphous silicon (48) to serve as a buffer between the metal back contact (46) and the intrinsic amorphous silicon layer (50). Another method of eliminating the Schottky junction completely replaces the metal back contact (46) and the N doped amorphous silicon layer (48) with a substitute material such as N doped poly-silicon (504, Figure 5).

    7.
    发明专利
    未知

    公开(公告)号:DE60035665D1

    公开(公告)日:2007-09-06

    申请号:DE60035665

    申请日:2000-12-13

    Applicant: XEROX CORP

    Abstract: A method and apparatus for reducing vertical leakage current in a high fill factor sensor array is described. Reduction of vertical leakage current is achieved by eliminating Schottky junction interfaces that occur between metal back contacts (46) and intrinsic amorphous silicon layers (50). One method of eliminating the Schottky junction uses an extra wide region of N doped amorphous silicon (48) to serve as a buffer between the metal back contact (46) and the intrinsic amorphous silicon layer (50). Another method of eliminating the Schottky junction completely replaces the metal back contact (46) and the N doped amorphous silicon layer (48) with a substitute material such as N doped poly-silicon (504, Figure 5).

    AMORPHOUS SILICON LAYER SENSOR AND METHOD OF FORMING SENSOR

    公开(公告)号:JP2001250935A

    公开(公告)日:2001-09-14

    申请号:JP2000400871

    申请日:2000-12-28

    Applicant: XEROX CORP

    Abstract: PROBLEM TO BE SOLVED: To provide a high fill factor image array which reduces the contact injection current to reduce the vertical leak current. SOLUTION: The sensor comprises an intrinsic amorphous silicon layer 50, p-doped silicon layer 52 coupled with a first surface of the intrinsic amorphous silicon layer 50, first transparent electrode 54 coupled with the p-doped silicon layer, and at least one nonmetal back contact 48 coupled with a second surface of the intrinsic amorphous silicon layer 50. The back contact 48 is intended to collect charges from one region of the intrinsic amorphous silicon layer 50, and to give the collected charges to a detecting electronic unit 108.

    IMAGE SENSOR HAVING PERFORMANCE ENHANCING STRUCTURE

    公开(公告)号:JP2003209239A

    公开(公告)日:2003-07-25

    申请号:JP2003000145

    申请日:2003-01-06

    Applicant: XEROX CORP

    Abstract: PROBLEM TO BE SOLVED: To provide a CMOS image sensor having a low crosstalk and a high light absorbance. SOLUTION: The image sensor includes inactivated walls 210 extended into the interior of a photosensor layer upwardly from pixel contact pads 113, and the pads 113 are isolated from each other to reduce crosstalk. In an embodiment, a metal structure, to which a negative bias is applied to prevent crosstalk and which is extended as far as the lower part of any of the contact pads to increase the capacities of the pixels, is provided in a lower part of an interface region for separating adjacent pixels. In an embodiment, not p-type dopants but another photodiode material is contained in a lower amorphous silicon photodiode layer. COPYRIGHT: (C)2003,JPO

    Buffered substrate foe semiconductor element
    10.
    发明专利
    Buffered substrate foe semiconductor element 审中-公开
    缓冲基底FOE半导体元件

    公开(公告)号:JP2009049428A

    公开(公告)日:2009-03-05

    申请号:JP2008272411

    申请日:2008-10-22

    Abstract: PROBLEM TO BE SOLVED: To provide a technique for finer and even particle size of polycrystal silicon without increasing manufacture time and cost. SOLUTION: Used for a semiconductor device wherein a silicon layer 104 formed on a substrate 100 is irradiated with a laser beam 106 for crystallization so that a polycrystal silicon layer 108 is obtained, a buffer layer 102 is formed between the substrate 100 and the silicon layer 104. Relating to such buffered substrate as containing the buffer layer 102, the buffer layer 102 has a melting point higher than the limit temperature of the substrate 100, in addition, at crystallization of the silicon layer 104, it regulates nucleus generation density of the silicon layer 104 for forming an even silicon crystal particles on the buffer layer 102, and functions as a base for isotropic particle growth in crystallization process of the silicon layer 104. COPYRIGHT: (C)2009,JPO&INPIT

    Abstract translation: 要解决的问题:提供一种在不增加制造时间和成本的情况下提供更精细甚至粒径的多晶硅的技术。 解决方案:用于其上形成在基板100上的硅层104用激光束106照射以进行结晶的半导体器件,从而获得多晶硅层108,在基板100和基板100之间形成缓冲层102 与含有缓冲层102的缓冲基板相比,缓冲层102的熔点高于基板100的极限温度,此外,在硅层104的结晶化时,其调节核产生 用于在缓冲层102上形成均匀的硅晶粒的硅层104的密度,并且作为硅层104的结晶过程中的各向同性粒子生长的基底起作用。(C)2009,JPO&INPIT

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