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    AUXILIARY ROM MEMORY SYSTEM
    1.
    发明专利
    AUXILIARY ROM MEMORY SYSTEM 未知

    公开(公告)号：CA1108768A

    公开(公告)日：1981-09-08

    申请号：CA359371

    申请日：1980-08-29

    Applicant: XEROX CORP

    Inventor： POST DONALD S ,  MAGER GEORGE E ,  NELSON FRANK M ,  REID STEVEN L ,  RICHARDSON PHILIP ,  ROCHAT VERNON E

    IPC: G06F13/00

    Abstract: AUXILIARY ROM MEMORY SYSTEM An auxiliary ROM memory system which is hierarchied for providing for the contingency of additional read-only memory control program storage requirements in excess or in lieu of the predetermined ROM memory provided on-board a microprocessor based central processing unit module, and a readonly memory altering capability utilizing programmable readonly memory to expedite the implementation/installation of changes to the ROM bit patterns. The alterable PROM storage comprises bulk PROM memory including a first PROM set that is mutually exclusive as to existing on-board ROM memory for addressably branching to code extensions and/or in-line code insertions, and/or a second PROM set that is mutually inclusive as to existent on-board and contigent ROM memory for decodably addressing large-scale code overlays thereto. In addition, the alterable PROM storage comprises patch PROM for addressing, through multi-leveled decoding, small-scale code overlays to the on-board and contingent ROM memory for single in-line bit pattern alterations. Conflicting memory requests involving addresses recognized by more than one of the supra memory categories, when enabled, are presented to a predetermined hierarchy of memory precedences for resolution thereof. Each of the enumerated memory categories of the auxiliary ROM memory system may be operative to have its population incremented or decremented without invalidating the above hierarchy of addressing.

    DIRECT MEMORY ACCESS REFRESH SYSTEM
    4.
    发明专利
    DIRECT MEMORY ACCESS REFRESH SYSTEM 未知

    公开(公告)号：CA1100645A

    公开(公告)日：1981-05-05

    申请号：CA294599

    申请日：1978-01-09

    Applicant: XEROX CORP

    Inventor： CRISWELL THOMAS ,  MAGER GEORGE E ,  NELSON FRANK M ,  GILLETT KENNETH ,  HOLT CHARLES P ,  STEINER EDWARD L ,  DAUGHTON JOHN W ,  FISKE KENTON W ,  HALL WARREN L

    IPC: G03G21/14 ,  G05B19/05 ,  G06F13/12 ,  G06F13/28 ,  G06F9/16

    Abstract: Direct Memory Access Refresh System In a controller for a host machine such as an electrostatographic copier having a central processing unit module connected via a system bus to an input-output processing unit module, a direct memory access system functioning as part of the input-output processing unit module and operative to provide a high-speed means of refreshing and updating control registers in the host machine by direct accessing of memory in the central processing unit module. The direct memory access system may be programmed to synchronously refresh-update the host machine's control registers as in its normal mode and also asynchronously refresh-update the control registers as in the abnormal mode of a detected electrical disturbance in the electro-sensitive periphery surrounding the control registers, thus requiring restoring thereof. High-speed movement of data by the direct memory access system is achieved through dedicating a portion of random access memory in the central processing unit module for such accessing, and transferring control of the system bus from the central processing unit module to the direct memory access system. This enables data accessed through a fixed sequence of addresses from dedicated memory to be transferred directly to the host machine's control registers without incurring time constants that would otherwise be had if the data were to be manipulated by a central processor in the central processing unit module

    AUXILIARY ROM MEMORY SYSTEM
    6.
    发明专利
    AUXILIARY ROM MEMORY SYSTEM 未知

    公开(公告)号：CA1108771A

    公开(公告)日：1981-09-08

    申请号：CA359374

    申请日：1980-08-29

    Applicant: XEROX CORP

    Inventor： POST DONALD S ,  MAGER GEORGE E ,  NELSON FRANK M ,  REID STEVEN L ,  RICHARDSON PHILIP ,  ROCHAT VERNON E

    IPC: G06F13/00

    Abstract: AUXILIARY ROM MEMORY SYSTEM An auxiliary ROM memory system which is hierarchied for providing for the contingency of additional read-only memory control program storage requirements in excess or in lieu of the predetermined ROM memory provided on-board a microprocessor based central processing unit module, and a readonly memory altering capability utilizing programmable readonly memory to expedite the implementation/installation of changes to the ROM bit patterns. The alterable PROM storage comprises bulk PROM memory including a first PROM set that is mutually exclusive as to existing on-board ROM memory for addressably branching to code extensions and/or in-line code insertions, and/or a second PROM set that is mutually inclusive as to existent on-board and contigent ROM memory for decodably addressing large-scale code overlays thereto. In addition, the alterable PROM storage comprises patch PROM for addressing, through multi-leveled decoding, small-scale code overlays to the on-board and contingent ROM memory for single in-line bit pattern alterations. Conflicting memory requests involving addresses recognized by more than one of the supra memory categories, when enabled, are presented to a predetermined hierarchy of memory precedences for resolution thereof. Each of the enumerated memory categories of the auxiliary ROM memory system may be operative to have its population incremented or decremented without invalidating the above hierarchy of addressing.

    AUXILIARY ROM MEMORY SYSTEM
    7.
    发明专利
    AUXILIARY ROM MEMORY SYSTEM 未知

    公开(公告)号：CA1100646A

    公开(公告)日：1981-05-05

    申请号：CA297329

    申请日：1978-02-20

    Applicant: XEROX CORP

    Inventor： POST DONALD S ,  MAGER GEORGE E ,  NELSON FRANK M ,  REID STEVEN L ,  RICHARDSON PHILIP ,  ROCHAT VERNON E

    IPC: G06F12/06 ,  G06F9/26 ,  G06F9/445 ,  G06F13/00

    Abstract: AUXILIARY ROM MEMORY SYSTEM An auxiliary ROM memory system which is hierarchied for providing for the contingency of additional read-only memory control program storage requirements in excess or in lieu of the predetermined ROM memory provided on-board a microprocessor based central processing unit module, and a readonly memory altering capability utilizing programmable readonly memory to expedite the implementation/installation of changes to the ROM bit patterns. The alterable PROM storage comprises bulk PROM memory including a first PROM set that is mutually exclusive as to existing on-board ROM memory for addressably branching to code extensions and/or in-line code insertions, and/or a second PROM set that is mutually inclusive as to existent on-board and contigent ROM memory for decodably addressing large-scale code overlays thereto. In addition, the alterable PROM storage comprises patch PROM for addressing, through multi-leveled decoding, small-scale code overlays to the on-board and contingent ROM memory for single in-line bit pattern alterations. Conflicting memory requests involving addresses recognized by more than one of the supra memory categories, when enabled, are presented to a predetermined hierarchy of memory precedences for resolution thereof. Each of the enumerated memory categories of the auxiliary ROM memory system may be operative to have its population incremented or decremented without invalidating the above hierarchy of addressing.

    Locally decoding clock control system - uses logic decoding element near switching device on chip for digital processors
    9.
    发明专利
    Locally decoding clock control system - uses logic decoding element near switching device on chip for digital processors 未知

    公开(公告)号：DE2827628A1

    公开(公告)日：1979-01-18

    申请号：DE2827628

    申请日：1978-06-23

    Applicant: XEROX CORP

    Inventor： MAGER GEORGE E

    IPC: G06F1/04 ,  G06F1/10

    Abstract: A distributive time control system is used in a digital processor system. There is at least one switching element driven by a command signal and a machine cycle clock signal has a locally decoding clock control on a semiconductor chip with a number of devices which it drives. It is designed to reduce the space on the chip occupied by clock signal distribution paths and push-pull drivers previously required to maintain correct logic levels. A time control device generates two or more clock signals which are combined into the desired machine cycle signal by a decoder placed near the switching element to be driven and contg. logic gates.

    AUXILIARY ROM MEMORY SYSTEM
    10.
    发明专利
    AUXILIARY ROM MEMORY SYSTEM 未知

    公开(公告)号：CA1108770A

    公开(公告)日：1981-09-08

    申请号：CA359373

    申请日：1980-08-29

    Applicant: XEROX CORP

    Inventor： POST DONALD S ,  MAGER GEORGE E ,  NELSON FRANK M ,  REID STEVEN L ,  RICHARDSON PHILIP ,  ROCHAT VERNON E

    IPC: G06F13/00

    Abstract: AUXILIARY ROM MEMORY SYSTEM An auxiliary ROM memory system which is hierarchied for providing for the contingency of additional read-only memory control program storage requirements in excess or in lieu of the predetermined ROM memory provided on-board a microprocessor based central processing unit module, and a readonly memory altering capability utilizing programmable readonly memory to expedite the implementation/installation of changes to the ROM bit patterns. The alterable PROM storage comprises bulk PROM memory including a first PROM set that is mutually exclusive as to existing on-board ROM memory for addressably branching to code extensions and/or in-line code insertions, and/or a second PROM set that is mutually inclusive as to existent on-board and contigent ROM memory for decodably addressing large-scale code overlays thereto. In addition, the alterable PROM storage comprises patch PROM for addressing, through multi-leveled decoding, small-scale code overlays to the on-board and contingent ROM memory for single in-line bit pattern alterations. Conflicting memory requests involving addresses recognized by more than one of the supra memory categories, when enabled, are presented to a predetermined hierarchy of memory precedences for resolution thereof. Each of the enumerated memory categories of the auxiliary ROM memory system may be operative to have its population incremented or decremented without invalidating the above hierarchy of addressing.

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