公开(公告)号：CA1096506A

公开(公告)日：1981-02-24

申请号：CA294544

申请日：1978-01-09

Applicant: XEROX CORP

Inventor： RICHARDSON PHILIP ,  CRISWELL THOMAS ,  STEINER EDWARD L ,  DAUGHTON JOHN W ,  FISKE KENTON W

IPC: G06F11/00 ,  G06F13/28

Abstract: AMETHYST CONTROLLER WATCH DOG TIMER In a controller for directing a host machine including a central processor for program execution, a system bus controlled by the central processor for carrying data, address, and control signals, a data memory coupled to the system bus, and a direct memory access module for conveyance through the system bus of a hold signal to the central processor upon receipt of an enabling signal, and upon acknowledgement for control assumptions of the system bus for generating address and state signals that will directly access the data memory for host machine update. In addition, a fault timer is included comprising a counter clocked at a given frequency for reset by the state signal from the direct memory access module if within a given period, and upon reset absence thereafter for generating a fault signal, and a bistable unit operative to receive the fault signal from said counter for clocked latching thereof, and for generating a hold signal through the direct memory access module to the central processor and a disabling signal to the host machine.

公开(公告)号：DE2800855A1

公开(公告)日：1978-07-13

申请号：DE2800855

申请日：1978-01-10

Applicant: XEROX CORP

Inventor： CRISWELL THOMAS ,  MAGER GEORGE E ,  NELSON FRANK M ,  GILLETT KENNETH ,  HOLT CHARLES P ,  STEINER EDWARD L ,  DAUGHTON JOHN W ,  FISKE KENTON W ,  HALL WARREN L

IPC: G03G21/14 ,  G05B19/05 ,  G06F13/12 ,  G06F13/28 ,  G06F9/00 ,  G05B19/04 ,  G06F13/06 ,  G06F15/46

公开(公告)号：DE2800892A1

公开(公告)日：1978-09-21

申请号：DE2800892

申请日：1978-01-10

Applicant: XEROX CORP

Inventor： GILLETT KENNETH ,  CRISWELL THOMAS ,  RICHARDSON PHILIP ,  FISKE KENTON W ,  STEINER EDWARD L ,  DAVIS KENNETH A ,  KUKUCKA WILLIAM P

IPC: G06F12/16 ,  G03G21/00 ,  G03G21/14 ,  G06F1/28 ,  G06F11/16 ,  G06F13/28 ,  G06F13/06 ,  G06F15/46 ,  G06F9/00 ,  G05B19/04

Abstract: A non-volatile storage module as utilized in a controller for directing a plurality of control registers of a host machine. The controller includes a central processor that is communicatively coupled through a system bus having control data, and address lines to the module and host machine. The non-volatile storage module includes a data memory operative to interface with the system bus for storing data, and for input-output of the data therefrom through the system bus upon command of the central processor. In addition, the module further includes a power storage unit coupled to the data memory for distributing a plurality of power signals from the host machine through a plurality of critical and non-critical power lines to the data memory for providing a power source that may be utilized therein for a power down condition and for sensing a power down condition on the critical power line from the power storage unit for the switching thereof to the data memory. The module also includes an apparatus that is operative upon indication of a power down condition from the host machine for generating an enabling signal to the data memory while a current address signal on the system bus is being received by the data memory.

公开(公告)号：CA1109158A

公开(公告)日：1981-09-15

申请号：CA294574

申请日：1978-01-09

Applicant: XEROX CORP

Inventor： GILLETT KENNETH ,  CRISWELL THOMAS ,  RICHARDSON PHILIP ,  STEINER EDWARD L ,  FISKE KENTON W ,  DAVIS KENNETH A ,  KUKUCKA WILLIAM P

IPC: G06F12/16 ,  G03G21/00 ,  G03G21/14 ,  G06F1/28 ,  G06F11/16 ,  G06F13/28 ,  G06F13/00

Abstract: NON-VOLATILE STORAGE MODULE FOR A CONTROLLER A non-volatile storage module as utilized in a controller for directing a plurality of control registers of a host machine. The controller including a central processor that is communicatively coupled through a system bus having control data, and address lines to the module and host machine. The non-volatile storage module includes a data memory operative to interface with the system bus for storing data, and for input-output of the data therefrom through the system bus upon command of the central processor. In addition, the module further includes a power storage unit coupled to the data memory for distributing a plurality of power signals from the host machine through a plurality of critical and non-critical power lines to the data memory for providing a power source that may be utilized therein for a power down condition and for sensing a power down condition on the critical power line from the power storage unit for the switching thereof to the data memory. The module also includes an apparatus that is operative upon indication of a power down condition from the host machine for generating an enabling signal to the data memory while a current address signal on the system bus is being received by the data memory.

公开(公告)号：CA1100645A

公开(公告)日：1981-05-05

申请号：CA294599

申请日：1978-01-09

Applicant: XEROX CORP

Inventor： CRISWELL THOMAS ,  MAGER GEORGE E ,  NELSON FRANK M ,  GILLETT KENNETH ,  HOLT CHARLES P ,  STEINER EDWARD L ,  DAUGHTON JOHN W ,  FISKE KENTON W ,  HALL WARREN L

IPC: G03G21/14 ,  G05B19/05 ,  G06F13/12 ,  G06F13/28 ,  G06F9/16

Abstract: Direct Memory Access Refresh System In a controller for a host machine such as an electrostatographic copier having a central processing unit module connected via a system bus to an input-output processing unit module, a direct memory access system functioning as part of the input-output processing unit module and operative to provide a high-speed means of refreshing and updating control registers in the host machine by direct accessing of memory in the central processing unit module. The direct memory access system may be programmed to synchronously refresh-update the host machine's control registers as in its normal mode and also asynchronously refresh-update the control registers as in the abnormal mode of a detected electrical disturbance in the electro-sensitive periphery surrounding the control registers, thus requiring restoring thereof. High-speed movement of data by the direct memory access system is achieved through dedicating a portion of random access memory in the central processing unit module for such accessing, and transferring control of the system bus from the central processing unit module to the direct memory access system. This enables data accessed through a fixed sequence of addresses from dedicated memory to be transferred directly to the host machine's control registers without incurring time constants that would otherwise be had if the data were to be manipulated by a central processor in the central processing unit module