公开(公告)号：WO2020190873A1

公开(公告)日：2020-09-24

申请号：PCT/US2020/022986

申请日：2020-03-16

Applicant: XILINX, INC.

Inventor： LEUNG, Caleb S. ,  LEE, Edward ,  WONG, Alan C. ,  BORRELLI, Christopher J. ,  FRANS, Yohan

IPC: H03L7/10 ,  H03L7/183 ,  H03L7/24

Abstract: Apparatus and associated methods relating to reducing lock time include pre-calibrating and storing phase-locked loop (PLL) and/or injection-locked oscillator (ILO) adaptation values during startup and loading the pre-calibrated values during rate change. In an illustrative example, an integrated circuit may include a controllable frequency circuit operable at frequencies within each of a plurality of frequency bands. A data store may store operational settings associated with each frequency of the plurality of frequency bands. A state machine may be coupled to the controllable frequency circuit and the data store configured to select a predetermined frequency band in response to a command signal, retrieve, from the data store, operational settings associated with the predetermined frequency band, and, apply the retrieved operational settings to the controllable frequency circuit. With the pre-calibration, PLL and/or ILO lock times during rate change in a multi-rate serializer/deserializer (SERDES) link may be advantageously reduced.

公开(公告)号：EP3918715A1

公开(公告)日：2021-12-08

申请号：EP20718080.3

申请日：2020-03-16

Applicant: Xilinx, Inc.

Inventor： LEUNG, Caleb S. ,  LEE, Edward ,  WONG, Alan C. ,  BORRELLI, Christopher J. ,  FRANS, Yohan

IPC: H03L7/10 ,  H03L7/183 ,  H03L7/24