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公开(公告)号：WO2018080652A1
公开(公告)日：2018-05-03
申请号：PCT/US2017/051379
申请日：2017-09-13
Applicant: XILINX, INC.
Inventor： ZHANG, Hongtao , WU, Zhaoyin D. , BORRELLI, Christopher J. , ZHANG, Geoffrey
Abstract: An example method of performing an eye-scan in a receiver includes: generating (104) digital samples from an analog signal input to the receiver based on a sampling clock, the sampling clock phase-shifted with respect to a reference clock based on a phase interpolator (PI) code; equalizing (204) the digital samples based on first equalization parameters of a plurality of equalization parameters of the receiver; adapting (404) the plurality of equalization parameters and performing clock recovery based on the digital samples to generate the PI code; and performing a plurality of cycles of locking (406) the plurality of equalization parameters, suspending (408) phase detection in the clock recovery, offsetting (410) the PI code, collecting (412) an output of the receiver, resuming (414) the phase detection in the clock recovery, and unlocking (414) the equalization parameters to perform the eye scan.
Abstract translation: 在接收器中执行眼睛扫描的示例方法包括：基于采样时钟从输入到接收器的模拟信号生成（104）数字采样，所述采样时钟的相位相移 以基于相位内插器（PI）码的参考时钟; 基于所述接收器的多个均衡参数的第一均衡参数来均衡（204）所述数字样本; 对所述多个均衡参数进行适配（404）并且基于所述数字样本执行时钟恢复以生成所述PI码; （406）所述多个均衡参数，在所述时钟恢复中暂停（408）相位检测，偏移（410）所述PI代码，收集（412）所述接收器的输出，恢复（414） 时钟恢复中的相位检测，以及解锁（414）均衡参数以执行眼部扫描。
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公开(公告)号：WO2020190873A1
公开(公告)日：2020-09-24
申请号：PCT/US2020/022986
申请日：2020-03-16
Applicant: XILINX, INC.
Inventor： LEUNG, Caleb S. , LEE, Edward , WONG, Alan C. , BORRELLI, Christopher J. , FRANS, Yohan
Abstract: Apparatus and associated methods relating to reducing lock time include pre-calibrating and storing phase-locked loop (PLL) and/or injection-locked oscillator (ILO) adaptation values during startup and loading the pre-calibrated values during rate change. In an illustrative example, an integrated circuit may include a controllable frequency circuit operable at frequencies within each of a plurality of frequency bands. A data store may store operational settings associated with each frequency of the plurality of frequency bands. A state machine may be coupled to the controllable frequency circuit and the data store configured to select a predetermined frequency band in response to a command signal, retrieve, from the data store, operational settings associated with the predetermined frequency band, and, apply the retrieved operational settings to the controllable frequency circuit. With the pre-calibration, PLL and/or ILO lock times during rate change in a multi-rate serializer/deserializer (SERDES) link may be advantageously reduced.
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公开(公告)号：EP3500867A1
公开(公告)日：2019-06-26
申请号：EP17777452.8
申请日：2017-09-13
Applicant: Xilinx, Inc.
Inventor： ZHANG, Hongtao , WU, Zhaoyin D. , BORRELLI, Christopher J. , ZHANG, Geoffrey
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公开(公告)号：EP3918715A1
公开(公告)日：2021-12-08
申请号：EP20718080.3
申请日：2020-03-16
Applicant: Xilinx, Inc.
Inventor： LEUNG, Caleb S. , LEE, Edward , WONG, Alan C. , BORRELLI, Christopher J. , FRANS, Yohan
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