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    DATA RECEIVERS AND METHODS OF IMPLEMENTING DATA RECEIVERS IN AN INTEGRATED CIRCUIT
    1.
    发明申请
    DATA RECEIVERS AND METHODS OF IMPLEMENTING DATA RECEIVERS IN AN INTEGRATED CIRCUIT 审中-公开
    数据接收器和在集成电路中实现数据接收器的方法

    公开(公告)号：WO2015094865A1

    公开(公告)日：2015-06-25

    申请号：PCT/US2014/069608

    申请日：2014-12-10

    Applicant: XILINX, INC.

    Inventor： HSIEH, Cheng-Hsiang ,  CHANG, Kun-Yung ,  SAVOJ, Jafar

    IPC: H04L7/00 ,  H04L7/033 ,  H04L25/03

    CPC classification number: H04L7/0025 ,  H04L7/0062 ,  H04L7/0331 ,  H04L7/0334 ,  H04L25/03057 ,  H04L25/03885

    Abstract: A data receiver implemented in an integrated circuit is described. The data receiver comprises an input (305) receiving a data signal; a first equalization circuit (304) coupled to receive the data signal, wherein the first equalization circuit is used to receive the data of the data signal; and a second equalization circuit (310) coupled to receive the data signal, wherein the second equalization circuit is used to adjust a clock phase offset.

    Abstract translation: 描述了在集成电路中实现的数据接收器。 数据接收机包括接收数据信号的输入端（305） 耦合以接收所述数据信号的第一均衡电路（304），其中所述第一均衡电路用于接收所述数据信号的数据; 以及耦合以接收所述数据信号的第二均衡电路（310），其中所述第二均衡电路用于调整时钟相位偏移。

    OFFSET CALIBRATION AND ADAPTIVE CHANNEL DATA SAMPLE POSITIONING
    2.
    发明申请
    OFFSET CALIBRATION AND ADAPTIVE CHANNEL DATA SAMPLE POSITIONING 审中-公开
    偏移校准和自适应通道数据样本定位

    公开(公告)号：WO2015030878A1

    公开(公告)日：2015-03-05

    申请号：PCT/US2014/033529

    申请日：2014-04-09

    Applicant: XILINX, INC.

    Inventor： JENKINS, Michael, O. ,  HSIEH, Cheng-Hsiang

    IPC: H04L7/033 ,  H04L25/06

    CPC classification number: H04L7/0334 ,  H04L25/069

    Abstract: A method of sample offset adjustment comprises providing edges associated with an asynchronous input to a receiver (201 ). The waveform edges are densely distributed across an adjustment range. At least a portion of the adjustment range is scanned for samples to obtain an error count (202). A first sample position is fixed, and a second sample position is moved across at least a portion of the adjustment range. A threshold bit error rate ("BER") is located from the scanning (203). An amount and a direction of a sample offset at the threshold BER from a reference location is determined (204). Either the first sample position or the second sample position is adjusted responsive to the amount and the direction of the sample offset to at least reduce the sample offset (205).

    Abstract translation: 一种采样偏移调整的方法包括将与异步输入相关联的边缘提供给接收器（201）。 波形边缘在调整范围内密集分布。 扫描样品的至少一部分调整范围以获得错误计数（202）。 第一采样位置是固定的，并且第二采样位置在调节范围的至少一部分上移动。 阈值误码率（“BER”）位于扫描（203）。 确定在参考位置处的阈值BER处的样本偏移的量和方向（204）。 响应于样品偏移的量和方向来调整第一样品位置或第二样品位置以至少减少样品偏移（205）。

    CLOCK DATA RECOVERY (CDR) PHASE WALK SCHEME IN A PHASE-INTERPOLATER-BASED TRANSCEIVER SYSTEM
    3.
    发明申请
    CLOCK DATA RECOVERY (CDR) PHASE WALK SCHEME IN A PHASE-INTERPOLATER-BASED TRANSCEIVER SYSTEM 审中-公开
    基于相位插座的收发系统中的时钟数据恢复（CDR）相位方案

    公开(公告)号：WO2017007522A1

    公开(公告)日：2017-01-12

    申请号：PCT/US2016/026681

    申请日：2016-04-08

    Applicant: XILINX, INC.

    Inventor： XU, Yu ,  HSIEH, Cheng-Hsiang ,  FRANS, Yohan ,  CHANG, Kun-Yung

    IPC: H04L7/00 ,  H03L7/081 ,  H04L7/033

    CPC classification number: H04L7/041 ,  H04L7/0025 ,  H04L7/0087 ,  H04L7/033 ,  H04L7/0337

    Abstract: Methods and apparatus are described for synchronously stepping at least one of a data phase interpolator (PI) code (306) or a crossing PI code (308) in a clock and data recovery (CDR) circuit (206) until one or more preset criteria are satisfied. One example method generally includes determining (502) that a condition has been met; based on the determination, stepping (504), in a CDR circuit (206), at least one of a data PI code (306) or a crossing PI code (308) for each cycle of a clock (302); stopping (506) the stepping based on one or more criteria to generate a predetermined state of the data PI code (306) and the crossing PI code (308), wherein the predetermined state comprises an offset between the data PI code (306) and the crossing PI code (308); receiving (508) a data stream (218); and performing (510) clock and data recovery on the data stream (218) based on the offset between the data PI code (306) and the crossing PI code (308).

    Abstract translation: 描述了用于在时钟和数据恢复（CDR）电路（206）中同时步进数据相位内插器（PI）代码（306）或交叉PI代码（308）中的至少一个的方法和装置，直到一个或多个预设标准 满意 一个示例性方法通常包括确定（502）已经满足条件; 基于对于每个时钟（302）的每个周期的数据PI代码（306）或交叉PI代码（308）中的至少一个，在CDR电路（206）中确定步骤（504）。 基于一个或多个标准来停止（506）步进，以产生数据PI代码（306）和交叉PI代码（308）的预定状态，其中预定状态包括数据PI代码（306）和 交叉PI代码（308）; 接收（508）数据流（218）; 并且基于数据PI代码（306）和交叉PI代码（308）之间的偏移，对数据流（218）执行（510）时钟和数据恢复。

    DIFFERENTIAL COMPARATOR CIRCUIT HAVING A WIDE COMMON MODE INPUT RANGE
    4.
    发明申请
    DIFFERENTIAL COMPARATOR CIRCUIT HAVING A WIDE COMMON MODE INPUT RANGE 审中-公开
    具有宽共通模式输入范围的差分比较器电路

    公开(公告)号：WO2011149691A1

    公开(公告)日：2011-12-01

    申请号：PCT/US2011/036540

    申请日：2011-05-13

    Applicant: XILINX, INC.

    Inventor： HSIEH, Cheng-Hsiang

    IPC: H03K5/24

    CPC classification number: H03K5/2481 ,  H03F3/4521

    Abstract: In one embodiment, a circuit arrangement is provided. The circuit arrangement includes a plurality of differential amplifiers (702), coupled in parallel, including at least a first differential amplifier and a second differential amplifier. Each differential amplifier includes an adjustable current control circuit (704) coupled to limit a tail current passing through the differential amplifier.

    Abstract translation: 在一个实施例中，提供电路装置。 电路装置包括并联耦合的多个差分放大器（702），至少包括第一差分放大器和第二差分放大器。 每个差分放大器包括耦合以限制通过差分放大器的尾电流的可调节电流控制电路（704）。

    DATA RECEIVERS AND METHODS OF IMPLEMENTING DATA RECEIVERS IN AN INTEGRATED CIRCUIT
    5.
    发明公开
    DATA RECEIVERS AND METHODS OF IMPLEMENTING DATA RECEIVERS IN AN INTEGRATED CIRCUIT 有权
    接收器和方法履行数据接收机在集成电路

    公开(公告)号：EP3085003A1

    公开(公告)日：2016-10-26

    申请号：EP14824648.1

    申请日：2014-12-10

    Applicant: Xilinx, Inc.

    Inventor： HSIEH, Cheng-Hsiang ,  CHANG, Kun-Yung ,  SAVOJ, Jafar

    IPC: H04L7/00 ,  H04L7/033 ,  H04L25/03

    CPC classification number: H04L7/0025 ,  H04L7/0062 ,  H04L7/0331 ,  H04L7/0334 ,  H04L25/03057 ,  H04L25/03885

    Abstract: A data receiver implemented in an integrated circuit is described. The data receiver comprises an input (305) receiving a data signal; a first equalization circuit (304) coupled to receive the data signal, wherein the first equalization circuit is used to receive the data of the data signal; and a second equalization circuit (310) coupled to receive the data signal, wherein the second equalization circuit is used to adjust a clock phase offset.

    Abstract translation: 上的集成电路中实现的数据接收器进行说明。 数据接收器输入接收的数据信号的步骤包括; 耦合以接收所述数据信号，worin第一均衡电路的第一均衡电路用于接收所述数据信号的所述数据; 和耦合以接收所述数据信号，worin第二均衡电路的第二均衡电路用于调整时钟相位偏移。

    CLOCK DATA RECOVERY (CDR) PHASE WALK SCHEME IN A PHASE-INTERPOLATER-BASED TRANSCEIVER SYSTEM
    10.
    发明公开
    CLOCK DATA RECOVERY (CDR) PHASE WALK SCHEME IN A PHASE-INTERPOLATER-BASED TRANSCEIVER SYSTEM 审中-公开
    基于相位插值的收发器系统中的时钟数据恢复（CDR）相位WALK方案

    公开(公告)号：EP3320644A1

    公开(公告)日：2018-05-16

    申请号：EP16718798.8

    申请日：2016-04-08

    Applicant: Xilinx, Inc.

    Inventor： XU, Yu ,  HSIEH, Cheng-Hsiang ,  FRANS, Yohan ,  CHANG, Kun-Yung

    IPC: H04L7/00 ,  H03L7/081 ,  H04L7/033

    CPC classification number: H04L7/041 ,  H04L7/0025 ,  H04L7/0087 ,  H04L7/033 ,  H04L7/0337

    Abstract: Methods and apparatus are described for synchronously stepping at least one of a data phase interpolator (PI) code or a crossing PI code in a clock and data recovery (CDR) circuit until one or more preset criteria are satisfied. One example method generally includes determining that a condition has been met; based on the determination, stepping, in a CDR circuit, at least one of a data PI code or a crossing PI code for each cycle of a clock; stopping the stepping based on one or more criteria to generate a predetermined state of the data PI code and the crossing PI code, wherein the predetermined state comprises an offset between the data PI code and the crossing PI code; receiving a data stream; and performing clock and data recovery on the data stream based on the offset between the data PI code and the crossing PI code.

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