公开(公告)号：WO2017209986A1

公开(公告)日：2017-12-07

申请号：PCT/US2017/033472

申请日：2017-05-19

Applicant: XILINX, INC.

Inventor： RAJ, Mayank ,  UPADHYAYA, Parag ,  BEKELE, Adebabay M.

IPC: H03L7/089 ,  H03L7/091

Abstract: An example a phase-locked loop (PLL) circuit (100) includes a sampling phase detector (103) configured to receive a reference clock and a feedback clock and configured to supply a first control current and a pulse signal. The PLL further includes a charge pump (107) configured to generate a second control current based on the first control current and the pulse signal. The PLL further includes a loop filter (109) configured to filter the second control current and generate an oscillator control voltage. The PLL further includes a voltage controlled oscillator (VCO) (1 16) configured to generate an output clock based on the oscillator control voltage. The PLL further includes a frequency divider (118) configured to generate the reference clock from the output clock.

Abstract translation: 一种锁相环（PLL）电路（100）的示例包括采样相位检测器（103），其被配置为接收参考时钟和反馈时钟并且被配置为提供第一控制电流和 脉冲信号。 PLL还包括电荷泵（107），电荷泵（107）被配置为基于第一控制电流和脉冲信号产生第二控制电流。 PLL还包括被配置为过滤第二控制电流并生成振荡器控制电压的环路滤波器（109）。 该PLL还包括被配置为基于该振荡器控制电压生成输出时钟的压控振荡器（VCO）（116）。 PLL还包括分频器（118），其被配置为从输出时钟生成参考时钟。

公开(公告)号：EP3465916A1

公开(公告)日：2019-04-10

申请号：EP17726468.6

申请日：2017-05-19

Applicant: Xilinx, Inc.

Inventor： RAJ, Mayank ,  UPADHYAYA, Parag ,  BEKELE, Adebabay M.

IPC: H03L7/089 ,  H03L7/091