公开(公告)号：WO2017131844A1

公开(公告)日：2017-08-03

申请号：PCT/US2016/062322

申请日：2016-11-16

Applicant: XILINX, INC.

Inventor： HEARNE, Catherine ,  UPADHYAYA, Parag ,  GEARY, Kevin

IPC: H03K5/135 ,  H03K5/00

CPC classification number: H03K5/135 ,  H03K2005/00052 ,  H03K2005/00058

Abstract: A phase interpolator implemented in an integrated circuit to generate a clock signal is described. The phase interpolator comprises a plurality of inputs (121) coupled to receive a plurality of clock signals; a plurality of transistor pairs (330, 332, 340, 342), each transistor pair having a first transistor coupled to a first output node (310) and a second transistor coupled to a second output node (314), wherein a first clock signal associated with the transistor pair is coupled to a gate of the first transistor and an inverted first clock signal associated with the transistor pair is coupled to a gate of the second transistor; a first active inductor load (308) coupled to the first output node; and a second active inductor load (312) coupled to the second output node.

Abstract translation: 描述了在集成电路中实现的用于生成时钟信号的相位内插器。 相位内插器包括多个输入端（121），其被耦合以接收多个时钟信号; 多个晶体管对（330,332,340,342），每个晶体管对具有耦合到第一输出节点（310）的第一晶体管和耦合到第二输出节点（314）的第二晶体管，其中第一时钟信号 与所述晶体管对相关联的所述第一时钟信号耦合到所述第一晶体管的栅极，并且与所述晶体管对相关联的反相的第一时钟信号耦合到所述第二晶体管的栅极; 耦合到第一输出节点的第一有源电感器负载（308） 和耦合到第二输出节点的第二有源电感负载（312）。

公开(公告)号：EP3408938B1

公开(公告)日：2019-07-03

申请号：EP16816469.7

申请日：2016-11-16

Applicant: Xilinx, Inc.

Inventor： HEARNE, Catherine ,  UPADHYAYA, Parag ,  GEARY, Kevin

IPC: H03K5/135 ,  H03K5/00

公开(公告)号：EP3408938A1

公开(公告)日：2018-12-05

申请号：EP16816469.7

申请日：2016-11-16

Applicant: Xilinx, Inc.

Inventor： HEARNE, Catherine ,  UPADHYAYA, Parag ,  GEARY, Kevin

IPC: H03K5/135 ,  H03K5/00

CPC classification number: H03K5/135 ,  H03K2005/00052 ,  H03K2005/00058

Abstract: A phase interpolator implemented in an integrated circuit to generate a clock signal is described. The phase interpolator comprises a plurality of inputs coupled to receive a plurality of clock signals; a plurality of transistor pairs, each transistor pair having a first transistor coupled to a first output node and a second transistor coupled to a second output node, wherein a first clock signal associated with the transistor pair is coupled to a gate of the first transistor and an inverted first clock signal associated with the transistor pair is coupled to a gate of the second transistor; a first active inductor load coupled to the first output node; and a second active inductor load coupled to the second output node.