公开(公告)号：WO2018057253A1

公开(公告)日：2018-03-29

申请号：PCT/US2017/049174

申请日：2017-08-29

Applicant: XILINX, INC.

Inventor： JING, Jing ,  WU, Shuxian ,  SOWARDS, Jane, W.

IPC: H01L21/761 ,  H01L21/8234

Abstract: An example a semiconductor device includes a first circuit (102) and a second circuit (104) formed in a semiconductor substrate (101). The semiconductor device further includes a first guard structure (106-1) formed in the semiconductor substrate and disposed between the first circuit and the second circuit, the first guard structure including first discontinuous pairs of n+ and p+ diffusions (108-1) disposed along a first axis. The semiconductor device further includes a second guard structure (106-2) formed in the semiconductor substrate and disposed between the first circuit and the second circuit, the second guard structure including second discontinuous pairs of n+ and p+ diffusions (108-2) disposed along the first axis, the second discontinuous pairs of n+ and p+ diffusions being staggered with respect to the first discontinuous pairs of n+ and p+ diffusions.

Abstract translation: 半导体器件的示例包括形成在半导体衬底（101）中的第一电路（102）和第二电路（104）。 该半导体器件进一步包括形成在半导体衬底中并设置在第一电路和第二电路之间的第一保护结构（106-1），第一保护结构包括沿着第一电极和第二电极布置的第一不连续的n +和p +扩散对（108-1） 第一轴。 该半导体器件进一步包括形成在半导体衬底中并设置在第一电路和第二电路之间的第二保护结构（106-2），第二保护结构包括沿着第一电极和第二电极布置的第二不连续对的n +和p +扩散（108-2） 第一轴，第二不连续对的n +和p +扩散相对于第一不连续对的n +和p +扩散交错。

公开(公告)号：WO2010087878A1

公开(公告)日：2010-08-05

申请号：PCT/US2009/057345

申请日：2009-09-17

Applicant: XILINX, INC.

Inventor： HO, Jung-Ching, J. ,  SOWARDS, Jane, W. ,  WU, Shuxian

IPC: H01L21/8234

CPC classification number: H01L21/823807 ,  H01L27/0207 ,  H01L27/11807 ,  H01L29/7843

Abstract: An integrated circuit (100) has a transistor with an active gate structure 108 overlying an active diffusion area 112 formed in a semiconductor substrate 126. A dummy gate structure 110 is formed over a diffusion area and separated from the active gate structure by a selected distance (d2). A stress layer (130) overlying the transistor array produces stress in a channel region (107) of the transistor.

Abstract translation: 集成电路（100）具有晶体管，其具有覆盖形成在半导体衬底126中的有源扩散区域112的有源栅极结构108.伪栅极结构110形成在扩散区域上，并与有源栅极结构分开一定距离 （D2）。 覆盖晶体管阵列的应力层（130）在晶体管的沟道区（107）中产生应力。

公开(公告)号：WO2003030009A3

公开(公告)日：2003-04-10

申请号：PCT/US2002/030240

申请日：2002-09-23

Applicant: XILINX, INC.

Inventor： DOUGLASS, Stephen, M. ,  YOUNG, Steven, P. ,  HERRON, Nigel, G. ,  VASHI, Mehul, R. ,  SOWARDS, Jane, W.

IPC: H03K19/177

Abstract: Interconnecting logic provides connectivity of an embedded fixed logic circuit, or circuits, with programmable logic fabric of a programmable gate array such that the fixed logic circuit functions as an extension of the programmable logic fabric. The interconnecting logic includes interconnecting tiles and may further include interfacing logic. The interconnecting tiles provide selective connectivity between inputs and/or outputs of the fixed logic circuit and the interconnects of the programmable logic fabric. The interfacing logic, when included, provides logic circuitry that conditions data transfers between the fixed logic circuit and the programmable logic fabric.

公开(公告)号：EP3501039A1

公开(公告)日：2019-06-26

申请号：EP17765322.7

申请日：2017-08-29

Applicant: Xilinx, Inc.

Inventor： JING, Jing ,  WU, Shuxian ,  SOWARDS, Jane, W.

IPC: H01L21/761 ,  H01L21/8234

Abstract: An example a semiconductor device includes a first circuit and a second circuit formed in a semiconductor substrate. The semiconductor device further includes a first guard structure formed in the semiconductor substrate and disposed between the first circuit and the second circuit, the first guard structure including first discontinuous pairs of n+ and p+ diffusions disposed along a first axis. The semiconductor device further includes a second guard structure formed in the semiconductor substrate and disposed between the first circuit and the second circuit, the second guard structure including second discontinuous pairs of n+ and p+ diffusions disposed along the first axis, the second discontinuous pairs of n+ and p+ diffusions being staggered with respect to the first discontinuous pairs of n+ and p+ diffusions.

公开(公告)号：EP3501039B1

公开(公告)日：2020-08-19

申请号：EP17765322.7

申请日：2017-08-29

Applicant: Xilinx, Inc.

Inventor： JING, Jing ,  WU, Shuxian ,  SOWARDS, Jane, W.

IPC: H01L29/06 ,  H01L21/761 ,  H01L21/8234