公开(公告)号：WO2018128733A1

公开(公告)日：2018-07-12

申请号：PCT/US2017/064022

申请日：2017-11-30

Applicant: XILINX, INC.

Inventor： UPADHYAYA, Parag ,  JING, Jing

IPC: H01L23/522

Abstract: An integrated circuit device is described. The integrated circuit device comprises a substrate (202); a plurality of metal routing interconnect layers (710, 712, 716); an inductor (108) formed in at least one metal layer of the plurality of metal routing interconnect layers; and a bottom metal layer (702) between the plurality of metal routing interconnect layers and the substrate; wherein a pattern ground shield (302) is formed in the bottom metal layer. A method of implementing an inductor in an integrated circuit device is also disclosed.

公开(公告)号：WO2018057253A1

公开(公告)日：2018-03-29

申请号：PCT/US2017/049174

申请日：2017-08-29

Applicant: XILINX, INC.

Inventor： JING, Jing ,  WU, Shuxian ,  SOWARDS, Jane, W.

IPC: H01L21/761 ,  H01L21/8234

Abstract: An example a semiconductor device includes a first circuit (102) and a second circuit (104) formed in a semiconductor substrate (101). The semiconductor device further includes a first guard structure (106-1) formed in the semiconductor substrate and disposed between the first circuit and the second circuit, the first guard structure including first discontinuous pairs of n+ and p+ diffusions (108-1) disposed along a first axis. The semiconductor device further includes a second guard structure (106-2) formed in the semiconductor substrate and disposed between the first circuit and the second circuit, the second guard structure including second discontinuous pairs of n+ and p+ diffusions (108-2) disposed along the first axis, the second discontinuous pairs of n+ and p+ diffusions being staggered with respect to the first discontinuous pairs of n+ and p+ diffusions.

Abstract translation: 半导体器件的示例包括形成在半导体衬底（101）中的第一电路（102）和第二电路（104）。 该半导体器件进一步包括形成在半导体衬底中并设置在第一电路和第二电路之间的第一保护结构（106-1），第一保护结构包括沿着第一电极和第二电极布置的第一不连续的n +和p +扩散对（108-1） 第一轴。 该半导体器件进一步包括形成在半导体衬底中并设置在第一电路和第二电路之间的第二保护结构（106-2），第二保护结构包括沿着第一电极和第二电极布置的第二不连续对的n +和p +扩散（108-2） 第一轴，第二不连续对的n +和p +扩散相对于第一不连续对的n +和p +扩散交错。

公开(公告)号：WO2021108037A1

公开(公告)日：2021-06-03

申请号：PCT/US2020/054891

申请日：2020-10-09

Applicant: XILINX, INC.

Inventor： JING, Jing ,  WU, Shuxian ,  WU, Xin X. ,  FRANS, Yohan

IPC: H01L23/522 ,  H01L23/58 ,  H01L23/64 ,  H01L23/66 ,  H01L25/065 ,  H01L23/00 ,  H01L21/768 ,  H01L23/48 ,  H01L23/528

Abstract: Examples described herein provide for an isolation design for an inductor of a stacked integrated circuit device. An example is a multi-chip device comprising a chip stack comprising: a plurality of chips, neighboring pairs of the plurality of chips being bonded together, each chip comprising a semiconductor substrate, and a front side dielectric layer on a front side of the semiconductor substrate; an inductor disposed in a backside dielectric layer of a first chip of the plurality of chips, the backside dielectric layer being on a backside of the semiconductor substrate of the first chip opposite from the front side of the semiconductor substrate of the first chip; and an isolation wall extending from the backside dielectric layer of the first chip to the front side dielectric layer, the isolation wall comprising a through substrate via of the first chip, the isolation wall being disposed around the inductor.

公开(公告)号：WO2016025260A1

公开(公告)日：2016-02-18

申请号：PCT/US2015/043747

申请日：2015-08-05

Applicant: XILINX, INC.

Inventor： JING, Jing ,  WU, Shuxian

IPC: H01L49/02 ,  H01L23/522

CPC classification number: H01L27/0805 ,  H01L23/5223 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In an example, a capacitor (120) in an integrated circuit (IC) (100), includes: a first finger capacitor (104a) formed in at least one layer (M6-M8) of the IC having a first bus (202a) and a second bus (204a); a second finger capacitor (104b) formed in the at least one layer of the IC having a first bus (202b) and a second bus (204b), where a longitudinal edge (230L) of the second bus of the second finger capacitor is adjacent a longitudinal edge (228R) of the first bus of the first finger capacitor and separated by a dielectric gap (118-1 ); and a first metal segment (214-1 ) formed on a first layer (M9) above the at least one layer, the first metal segment being electrically coupled to the first bus of the first finger capacitor and increasing a width and a height of the first bus of the first finger capacitor.

Abstract translation: 在一个示例中，集成电路（IC）（100）中的电容器（120）包括：形成在具有第一总线（202a）的IC的至少一个层（M6-M8）中的第一指状电容器（104a） 和第二总线（204a）; 形成在具有第一总线（202b）和第二总线（204b）的IC的至少一个层中的第二指状电容器（104b），其中第二指状电容器的第二总线的纵向边缘（230L）相邻 所述第一指状电容器的所述第一总线的纵向边缘（228R）由电介质间隙（118-1）分隔开; 以及形成在所述至少一层上方的第一层（M9）上的第一金属段（214-1），所述第一金属段电耦合到所述第一指状电容器的第一总线，并且增加所述第一金属段的宽度和高度 第一手指电容的总线。

公开(公告)号：WO2015080770A1

公开(公告)日：2015-06-04

申请号：PCT/US2014/046021

申请日：2014-07-09

Applicant: XILINX, INC.

Inventor： JING, Jing ,  WU, Shuxian ,  WU, Zhaoyin, D.

IPC: H01L27/01 ,  H01L23/522 ,  H01L49/02 ,  H05K1/16 ,  H03H7/01

CPC classification number: H03H7/0115 ,  H01L23/5223 ,  H01L23/5227 ,  H01L27/016 ,  H01L28/10 ,  H01L28/60 ,  H01L28/88 ,  H01L2924/0002 ,  H03H5/02 ,  H03H7/0138 ,  H05K1/16 ,  Y10T29/49117 ,  H01L2924/00

Abstract: A circuit includes a first finger capacitor (100) having a first bus line (110) coupled to a first plurality of finger elements (120) and a second bus line (105) coupled to a second plurality of finger elements (115). The first bus line is parallel to the second bus line. The circuit further includes an inductor (500) having a first leg (125, 515) oriented perpendicular to the first bus line and the second bus line. The first leg of the inductor is coupled to a center (135) of the first bus line. Related methods are also disclosed.

Abstract translation: 电路包括具有耦合到第一多个指状元件（120）的第一总线线路（110）和耦合到第二多个指状元件（115）的第二总线线路（105））的第一手指电容器（100）。 第一条总线与第二条总线平行。 电路还包括具有垂直于第一总线和第二总线定向的第一支脚（125,515）的电感器（500）。 电感器的第一支路耦合到第一总线的中心（135）。 还公开了相关方法。

公开(公告)号：WO2018053137A1

公开(公告)日：2018-03-22

申请号：PCT/US2017/051574

申请日：2017-09-14

Applicant: XILINX, INC.

Inventor： JING, Jing ,  WU, Shuxian ,  WU, Xin, X. ,  UPADHYAYA, Parag

IPC: H01L23/522

CPC classification number: H01L23/5227 ,  H01L23/5225 ,  H01L23/645 ,  H01L28/10

Abstract: A semiconductor device (300) includes an interconnect structure (306) disposed over a semiconductor substrate ( 302). The interconnect structure includes a first device (330) disposed in a first portion (306-1 ) of the interconnect structure. A first shielding plane (402) including a first conductive material is disposed in a second portion (306-2) of the interconnect structure over the first portion of the interconnect structure. A second device (504) is disposed in a third portion (306-3) of the interconnect structure over the second portion of the interconnect structure. An isolation wall (320) including a second conductive material is disposed in the first, second, and third portions of the interconnect structure. The isolation wall is coupled to the first shielding plane, and surrounds the first device, the first shielding plane, and the second device.

Abstract translation: 半导体器件（300）包括设置在半导体衬底（302）上的互连结构（306）。 互连结构包括布置在互连结构的第一部分（306-1）中的第一器件（330）。 包括第一导电材料的第一屏蔽平面（402）设置在互连结构的第一部分上的互连结构的第二部分（306-2）中。 第二器件（504）设置在互连结构的第二部分上方的互连结构的第三部分（306-3）中。 包括第二导电材料的隔离壁（320）设置在互连结构的第一部分，第二部分和第三部分中。 隔离壁耦合到第一屏蔽平面，并围绕第一装置，第一屏蔽平面和第二装置。

公开(公告)号：WO2014065905A1

公开(公告)日：2014-05-01

申请号：PCT/US2013/049319

申请日：2013-07-03

Applicant: XILINX, INC.

Inventor： JING, Jing ,  WU, Shuxian ,  UPADHYAYA, Parag

IPC: H01L49/02 ,  H01L23/522 ,  H01L23/64 ,  H01F17/00

CPC classification number: H01L28/10 ,  H01F17/0013 ,  H01L23/5227 ,  H01L23/645 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An inductor structure implemented within a semiconductor integrated circuit (IC) includes a coil (105) of conductive material including at least one turn and a current return (130, 500) encompassing the coil. The current return is formed of a plurality of interconnected metal layers (510, 515, 520, 525) of the semiconductor integrated circuit.

Abstract translation: 在半导体集成电路（IC）内实现的电感器结构包括包括至少一个匝的导电材料的线圈（105）和包围线圈的电流返回（130,500）。 电流返回由半导体集成电路的多个互连金属层（510,515,520,525）形成。

公开(公告)号：WO2012128832A1

公开(公告)日：2012-09-27

申请号：PCT/US2012/021079

申请日：2012-01-12

Applicant: XILINX, INC. ,  WU, Zhaoyin, D. ,  JIANG, Xuewen ,  UPADHYAYA, Parag ,  JING, Jing ,  WU, Shuxian

Inventor： WU, Zhaoyin, D. ,  JIANG, Xuewen ,  UPADHYAYA, Parag ,  JING, Jing ,  WU, Shuxian

IPC: H01L23/522

CPC classification number: H01L23/5227 ,  H01L23/5225 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An inductor structure (105, 500, 900) implemented within a semiconductor integrated circuit (IC) can include a coil (205, 505, 905) of conductive material that includes a center terminal (140, 510, 910) located at a midpoint of a length of the coil. The coil can be symmetrical with respect to a centerline (225, 535, 935) bisecting the center terminal. The coil can include a first differential terminal (210, 515, 915) and a second differential terminal (215, 520, 920). The inductor structure can include a return line (155, 560, 960) of conductive material positioned on the center line. The inductor structure can include an isolation ring (220, 525, 945) surrounding the coil. The inductor structure can include a patterned ground shield comprising a plurality of fingers (935, 1035) implemented within an IC process layer located between the coil (905) and a substrate (955) of the IC. The inductor structure can include an isolation wall (1 150) comprising a high conductive material formed to encompass the coil and the patterned ground shield. The isolation wall can be coupled to one end of each finger of the patterned ground shield.

Abstract translation: 实现在半导体集成电路（IC）内的电感器结构（105,500,900）可以包括导电材料的线圈（205,505,905），其包括位于中间端子（140,510,910）的中点 线圈的长度。 线圈可相对于将中心线平分的中心线（225,535,935）对称。 线圈可以包括第一差分端子（210,515,915）和第二差分端子（215,520,920）。 电感器结构可以包括位于中心线上的导电材料的返回线（155,560,960）。 电感器结构可以包括围绕线圈的隔离环（220,525,945）。 电感器结构可以包括图案化的接地屏蔽，其包括在位于线圈（905）和IC的衬底（955）之间的IC处理层内实现的多个指状物（935,1035）。 电感器结构可以包括隔离壁（115），其包括形成为包围线圈和图案化接地屏蔽的高导电材料。 隔离壁可以连接到图案化的接地屏蔽的每个手指的一端。

公开(公告)号：EP3501039B1

公开(公告)日：2020-08-19

申请号：EP17765322.7

申请日：2017-08-29

Applicant: Xilinx, Inc.

Inventor： JING, Jing ,  WU, Shuxian ,  SOWARDS, Jane, W.

IPC: H01L29/06 ,  H01L21/761 ,  H01L21/8234

公开(公告)号：EP4066281A1

公开(公告)日：2022-10-05

申请号：EP20800413.5

申请日：2020-10-09

Applicant: Xilinx, Inc.

Inventor： JING, Jing ,  WU, Shuxian ,  WU, Xin X. ,  FRANS, Yohan

IPC: H01L23/522 ,  H01L23/58 ,  H01L23/64 ,  H01L23/66 ,  H01L25/065 ,  H01L23/00 ,  H01L21/768 ,  H01L23/48 ,  H01L23/528