公开(公告)号：WO2015080770A1

公开(公告)日：2015-06-04

申请号：PCT/US2014/046021

申请日：2014-07-09

Applicant: XILINX, INC.

Inventor： JING, Jing ,  WU, Shuxian ,  WU, Zhaoyin, D.

IPC: H01L27/01 ,  H01L23/522 ,  H01L49/02 ,  H05K1/16 ,  H03H7/01

CPC classification number: H03H7/0115 ,  H01L23/5223 ,  H01L23/5227 ,  H01L27/016 ,  H01L28/10 ,  H01L28/60 ,  H01L28/88 ,  H01L2924/0002 ,  H03H5/02 ,  H03H7/0138 ,  H05K1/16 ,  Y10T29/49117 ,  H01L2924/00

Abstract: A circuit includes a first finger capacitor (100) having a first bus line (110) coupled to a first plurality of finger elements (120) and a second bus line (105) coupled to a second plurality of finger elements (115). The first bus line is parallel to the second bus line. The circuit further includes an inductor (500) having a first leg (125, 515) oriented perpendicular to the first bus line and the second bus line. The first leg of the inductor is coupled to a center (135) of the first bus line. Related methods are also disclosed.

Abstract translation: 电路包括具有耦合到第一多个指状元件（120）的第一总线线路（110）和耦合到第二多个指状元件（115）的第二总线线路（105））的第一手指电容器（100）。 第一条总线与第二条总线平行。 电路还包括具有垂直于第一总线和第二总线定向的第一支脚（125,515）的电感器（500）。 电感器的第一支路耦合到第一总线的中心（135）。 还公开了相关方法。

公开(公告)号：WO2016176205A1

公开(公告)日：2016-11-03

申请号：PCT/US2016/029361

申请日：2016-04-26

Applicant: XILINX, INC.

Inventor： UPADHYAYA, Parag ,  BEKELE, Adebabay, M. ,  TURKER MELEK, Didem, Z. ,  WU, Zhaoyin, D.

IPC: H03L7/18 ,  H03L7/197

CPC classification number: H03L7/095 ,  H03L7/18 ,  H03L7/197 ,  H03L7/1974 ,  H03M3/30 ,  H04B1/50

Abstract: In an example, a phase-locked loop (PLL) circuit (108) includes an error detector (202) operable to generate an error signal; an oscillator (204) operable to provide an output signal having an output frequency based on the error signal and a frequency band select signal, the output frequency being a frequency multiplier times a reference frequency; a frequency divider (208) operable to divide the output frequency of the output signal to generate a feedback signal based on a divider control signal; a sigma-delta modulator (SDM) (209) operable to generate the divider control signal based on inputs indicative of an integer value and a fractional value of the frequency multiplier, the SDM responsive to an order select signal operable to select an order of the SDM; and a state machine (214) operable to, in an acquisition state, generate the frequency band select signal and set the order of the SDM.

Abstract translation: 在一个示例中，锁相环（PLL）电路（108）包括可操作以产生误差信号的误差检测器（202） 振荡器（204），其可操作以提供具有基于所述误差信号和频带选择信号的输出频率的输出信号，所述输出频率是倍频器乘以参考频率; 分频器（208），其可操作以分割所述输出信号的输出频率以基于分频器控制信号产生反馈信号; Σ-Δ调制器（SDM）（209），其可操作以基于表示所述倍频器的整数值和分数值的输入产生所述除法器控制信号，所述SDM响应于可操作以选择所述乘法器的顺序的顺序选择信号 SDM; 以及状态机（214），其可操作以在获取状态下生成所述频带选择信号并设置所述SDM的顺序。

公开(公告)号：WO2013036306A1

公开(公告)日：2013-03-14

申请号：PCT/US2012/039898

申请日：2012-05-29

Applicant: XILINX, INC. ,  WU, Zhaoyin, D. ,  UPADHYAYA, Parag ,  JIANG, Xuewen

Inventor： WU, Zhaoyin, D. ,  UPADHYAYA, Parag ,  JIANG, Xuewen

IPC: H01L49/02

CPC classification number: H01L28/86 ,  Y10T29/43

Abstract: An interdigitated capacitor having digits of varying width is disclosed. One embodiment of a capacitor (100) includes a first plurality of conductive digits (110) and a second plurality of conductive digits (110) positioned in an interlocking manner with the first plurality of conductive digits (110), such that an interdigitated structure is formed. The first plurality of conductive digits (110) and the second plurality of conductive digits (110) collectively form a set of digits, where the width of a first digit in the set of digits (110) is non-uniform with respect to a second digit in the set of digits.

Abstract translation: 公开了具有变化宽度的数字的交错电容器。 电容器（100）的一个实施例包括与第一多个导电数字（110）以互锁方式定位的第一多个导电数字（110）和第二多个导电数字（110），使得叉指式结构 形成。 第一多个导电数字（110）和第二多个导电数字（110）共同形成一组数字，其中数字组（110）中的第一数字的宽度相对于第二数字（110）是不均匀的 数字组中的数字。

公开(公告)号：WO2019143431A1

公开(公告)日：2019-07-25

申请号：PCT/US2018/065826

申请日：2018-12-14

Applicant: XILINX, INC.

Inventor： WU, Zhaoyin, D. ,  UPADHYAYA, Parag ,  CHANG, Kun-Yung

IPC: H01L23/522

Abstract: Examples herein describe techniques for isolating portions of an IC (100) that include sensitive components (e.g., inductors or capacitors) from return current (330) in a grounding plane (415). An output current generated by a transmitter (105) or driver in an IC can generate a magnetic field (405) which induces return current in the grounding plane. If the return current is proximate the sensitive components (305), the return current can inject noise which can negatively impact other components in the IC. To isolate the sensitive components from the return current, embodiments herein include forming slots (500) through the grounding structure which includes the grounding plane on one or more sides of the sensitive components.

公开(公告)号：WO2012128832A1

公开(公告)日：2012-09-27

申请号：PCT/US2012/021079

申请日：2012-01-12

Applicant: XILINX, INC. ,  WU, Zhaoyin, D. ,  JIANG, Xuewen ,  UPADHYAYA, Parag ,  JING, Jing ,  WU, Shuxian

Inventor： WU, Zhaoyin, D. ,  JIANG, Xuewen ,  UPADHYAYA, Parag ,  JING, Jing ,  WU, Shuxian

IPC: H01L23/522

CPC classification number: H01L23/5227 ,  H01L23/5225 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An inductor structure (105, 500, 900) implemented within a semiconductor integrated circuit (IC) can include a coil (205, 505, 905) of conductive material that includes a center terminal (140, 510, 910) located at a midpoint of a length of the coil. The coil can be symmetrical with respect to a centerline (225, 535, 935) bisecting the center terminal. The coil can include a first differential terminal (210, 515, 915) and a second differential terminal (215, 520, 920). The inductor structure can include a return line (155, 560, 960) of conductive material positioned on the center line. The inductor structure can include an isolation ring (220, 525, 945) surrounding the coil. The inductor structure can include a patterned ground shield comprising a plurality of fingers (935, 1035) implemented within an IC process layer located between the coil (905) and a substrate (955) of the IC. The inductor structure can include an isolation wall (1 150) comprising a high conductive material formed to encompass the coil and the patterned ground shield. The isolation wall can be coupled to one end of each finger of the patterned ground shield.

Abstract translation: 实现在半导体集成电路（IC）内的电感器结构（105,500,900）可以包括导电材料的线圈（205,505,905），其包括位于中间端子（140,510,910）的中点 线圈的长度。 线圈可相对于将中心线平分的中心线（225,535,935）对称。 线圈可以包括第一差分端子（210,515,915）和第二差分端子（215,520,920）。 电感器结构可以包括位于中心线上的导电材料的返回线（155,560,960）。 电感器结构可以包括围绕线圈的隔离环（220,525,945）。 电感器结构可以包括图案化的接地屏蔽，其包括在位于线圈（905）和IC的衬底（955）之间的IC处理层内实现的多个指状物（935,1035）。 电感器结构可以包括隔离壁（115），其包括形成为包围线圈和图案化接地屏蔽的高导电材料。 隔离壁可以连接到图案化的接地屏蔽的每个手指的一端。

公开(公告)号：WO2016190923A1

公开(公告)日：2016-12-01

申请号：PCT/US2016/016872

申请日：2016-02-05

Applicant: XILINX, INC.

Inventor： LIAO, Yu ,  ZHANG, Geoffrey ,  ZHANG, Hongtao ,  CHANG, Kun-yung ,  PHAM, Toan ,  WU, Zhaoyin, D.

IPC: H04L25/03

CPC classification number: H04L27/3809 ,  H04L25/03057 ,  H04L25/03885

Abstract: A receiver (100) relates generally to channel adaptation. In this receiver (100), a first signal processing block (101) is coupled to a communications channel (20). The first signal processing block (101) includes: an AGC block (102) and a CTLE block (103) for receiving a modulated signal (21) for providing an analog signal (104); an ADC (105) for converting the analog signal (104) to digital samples (106); and an FFE block (112) for equalizing the digital samples (106) to provide equalized samples (114). A second signal processing block (111) includes: a DFE block (113) for receiving the equalized samples (114) for providing re-equalized samples (116); and a slicer (123) coupled to the DFE block (113) for slicing the re-equalized samples (116). A receiver adaptation block (150) is coupled to the first signal processing block (101) and the second signal processing block (111). The receiver adaptation block (150) is configured for providing an AGC adaptation, a CTLE adaptation, and a slicer adaptation to the communications channel (20).

Abstract translation: 接收机（100）一般涉及信道适配。 在该接收机（100）中，第一信号处理块（101）耦合到通信信道（20）。 第一信号处理块（101）包括：AGC块（102）和用于接收用于提供模拟信号（104）的调制信号（21））的CTLE块（103）。 用于将模拟信号（104）转换成数字样本（106）的ADC（105）; 以及用于均衡数字样本（106）以提供均衡样本（114）的FFE块（112）。 第二信号处理块（111）包括：DFE块（113），用于接收用于提供重新均衡的样本（116）的均衡样本（114）; 以及耦合到所述DFE块（113）的限幅器（123），用于对所述重新平衡样本（116）进行切片。 接收机适配块（150）耦合到第一信号处理块（101）和第二信号处理块（111）。 接收机适配块（150）被配置用于提供AGC适配，CTLE适配以及对通信信道（20）的限幅器适配。

公开(公告)号：WO2016168648A1

公开(公告)日：2016-10-20

申请号：PCT/US2016/027825

申请日：2016-04-15

Applicant: XILINX, INC.

Inventor： ZHANG, Hongtao ,  ZHANG, Geoffrey ,  SATARZADEH, Patrick ,  WU, Zhaoyin, D.

IPC: H04L25/06

CPC classification number: H04L27/06 ,  H04L25/061

Abstract: A circuit for receiving data in an integrated circuit is described. The circuit comprises a receiver (304) configured to receive an input signal and to generate output data based upon the input signal, the receiver having a level detection circuit (310) coupled to receive the input signal; and a calibration circuit (308) coupled to the receiver, the calibration circuit having an input (306) for receiving the input signal; an error detection circuit (31 1 ) coupled to the input, the error detection circuit coupled to receive the input signal, a first reference voltage and a second reference voltage; and a control circuit (340) coupled to an output of the error detection circuit, wherein the control circuit selectively generates either an offset control signal or an amplitude control signal based upon comparisons of the input signal to the first reference voltage and the second reference voltage. A method of receiving data is also disclosed.

Abstract translation: 描述用于在集成电路中接收数据的电路。 所述电路包括被配置为接收输入信号并基于所述输入信号产生输出数据的接收器（304），所述接收机具有耦合以接收所述输入信号的电平检测电路（310） 以及耦合到所述接收器的校准电路（308），所述校准电路具有用于接收所述输入信号的输入（306）; 耦合到所述输入的误差检测电路（31 1），所述误差检测电路被耦合以接收所述输入信号，第一参考电压和第二参考电压; 以及耦合到所述误差检测电路的输出的控制电路（340），其中所述控制电路基于所述输入信号与所述第一参考电压和所述第二参考电压的比较选择性地产生偏移控制信号或幅度控制信号 。 还公开了接收数据的方法。

公开(公告)号：EP3740969A1

公开(公告)日：2020-11-25

申请号：EP18847168.4

申请日：2018-12-14

Applicant: Xilinx, Inc.

Inventor： WU, Zhaoyin, D. ,  UPADHYAYA, Parag ,  CHANG, Kun-Yung

IPC: H01L23/522

公开(公告)号：EP3289687A1

公开(公告)日：2018-03-07

申请号：EP16723574.6

申请日：2016-04-26

Applicant: Xilinx, Inc.

Inventor： UPADHYAYA, Parag ,  BEKELE, Adebabay, M. ,  TURKER MELEK, Didem, Z. ,  WU, Zhaoyin, D.

IPC: H03L7/18 ,  H03L7/197

Abstract: In an example, a phase-locked loop (PLL) circuit includes an error detector operable to generate an error signal; an oscillator operable to provide an output signal having an output frequency based on the error signal and a frequency band select signal, the output frequency being a frequency multiplier times a reference frequency; a frequency divider operable to divide the output frequency of the output signal to generate a feedback signal based on a divider control signal; a sigma-delta modulator (SDM) operable to generate the divider control signal based on inputs indicative of an integer value and a fractional value of the frequency multiplier, the SDM responsive to an order select signal operable to select an order of the SDM; and a state machine operable to, in an acquisition state, generate the frequency band select signal and set the order of the SDM.

公开(公告)号：EP3289687B1

公开(公告)日：2019-12-18

申请号：EP16723574.6

申请日：2016-04-26

Applicant: Xilinx, Inc.

Inventor： UPADHYAYA, Parag ,  BEKELE, Adebabay, M. ,  TURKER MELEK, Didem, Z. ,  WU, Zhaoyin, D.

IPC: H03L7/18 ,  H03L7/197