公开(公告)号：JPH04150418A

公开(公告)日：1992-05-22

申请号：JP27359790

申请日：1990-10-12

Applicant: YAMAHA CORP

Inventor： KADAKA TAKAYUKI ,  MOTOME MITSUHIRO ,  HIRANO MASAZO ,  KISHII TATSUYA ,  MORITA KUNIAKI ,  HOSHI JURO

IPC: H03M3/04 ,  H03H17/00 ,  H03H17/02 ,  H03M3/02 ,  H03M7/00

Abstract: PURPOSE:To obtain a low-noise analog output by frequency-dividing a system clock signal having a frequency fs into

公开(公告)号：JPH04115713A

公开(公告)日：1992-04-16

申请号：JP23519390

申请日：1990-09-05

Applicant: YAMAHA CORP

Inventor： KADAKA TAKAYUKI ,  MOTOME MITSUHIRO ,  HIRANO MASAZO ,  KISHII TATSUYA ,  MORITA KUNIAKI ,  HOSHI JURO

IPC: H03M1/10 ,  H03K5/00

Abstract: PURPOSE:To obtain a pulse output with much less noise by interposing 2nd and 3rd transistors(TRs) turned on in response to a synchronizing pulse with a narrower pulse width than that of a data pulse in series between an output terminal and a 1st TR turned on in response to the data pulse. CONSTITUTION:With a digital signal (P) set to '1', TR T1 is turned on and a TR T6 is turned off, a clock signal phib goes to '1' and then TRs T2, T3 are turned on and a TR T4 is turned off. Then the signals P, phib go both to '1', the TRs T1-T3 are all tuned on and an output Q goes to 0. In this case, the period when the output Q takes 0 depends on the pulse width of the signal phib. The noise attended with a level change is blocked by the TRs T2, T3 in the off state even when the signal (P) 12 (when the TRs T2, T3 are turned off and the TR T4 is turned on) signal phib and the noise does not appear at the output Q. Thus, a wave shaping output C with less noise is obtained.

公开(公告)号：JPH10107564A

公开(公告)日：1998-04-24

申请号：JP25902196

申请日：1996-09-30

Applicant: YAMAHA CORP

Inventor： MORITA KUNIAKI ,  NORO MASAO

IPC: H03G3/12 ,  G10H1/08 ,  H03G3/00

Abstract: PROBLEM TO BE SOLVED: To provide a mixer circuit that mixes a plurality of signals with a high S/N in a simple configuration without distorting the waveform. SOLUTION: Upon the receipt of inpvut signals V1-V5, they are mixed in response to ratios R1-R5 and the mixed signal is fed to a noninverting input terminal of a 1st operational amplifier OP1. The 1st operational amplifier OP1 acts like a noninverter amplifier, and a 2nd operational amplifier OP2 acts like an inverter amplifier. The gain of the 2nd operational amplifier OP2 is controlled through the selection of switches SWa-SWe. Thus, a level of an inverted output signal Vout is adjusted and the result is added to the input. In this case, since two of the SWa-SWe are closed simultaneously, the level is adjusted in detail without distorting the output signal Vout.

公开(公告)号：JPH04111521A

公开(公告)日：1992-04-13

申请号：JP22918090

申请日：1990-08-30

Applicant: YAMAHA CORP

Inventor： KADAKA TAKAYUKI ,  MOTOME MITSUHIRO ,  HIRANO MASAZO ,  HOSHI JURO ,  KISHII TATSUYA ,  MORITA KUNIAKI

IPC: H03M1/10 ,  H03K5/00

Abstract: PURPOSE:To obtain a pulse output of less noise from an output element by interposing a second transistor TR, which is turned on in accordance with a synchronizing pulse narrower than a data pulse, between an output terminal and a first TR turned on in accordance with the data pulse. CONSTITUTION:A first TR T1 turned on in accordance with the data pulse and a second TR T2 turned on in accordance with the synchronizing pulse narrower than the data pulse are connected in series, and the output terminal is connected to the side of the second TR T3 of this series connection line, and the pulse output of small noise synchronized with the turning-on timing of the second TR T3 is taken out from the output terminal on condition that first and second TRs T2 and T3 are turned on together. That is, the noise accompanied with the level change of the data pulse is stopped by the second TR T3 and does not reach the output, terminal because the second TR T3 is interposed in the turning-off state between the first TR. T1 and the output terminal. Thus, a pulse output Q of less noise is obtained from the output terminal.

公开(公告)号：JPH04179233A

公开(公告)日：1992-06-25

申请号：JP30790390

申请日：1990-11-14

Applicant: YAMAHA CORP

Inventor： KADAKA TAKAYUKI ,  MOTOME MITSUHIRO ,  HIRANO MASAZO ,  HOSHI JURO ,  KISHII TATSUYA ,  MORITA KUNIAKI

IPC: H01L23/52 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/822 ,  H01L23/522 ,  H01L27/04

Abstract: PURPOSE:To restrain an electromagnetic noise from coming in and out by a method wherein an interconnection at a lower layer than the uppermost layer out of multilayer interconnections is used as an interconnection for an electromagnetic noise radiation circuit or the like, a conductive layer for electromagnetic shielding use is formed in the same layer level as that of an interconnection at the uppermost layer and the conductive layer is connected to any power-supply terminal. CONSTITUTION:First-layer interconnections 12C, 12D and the like are used as interconnections for a first circuit; second-layer interconnections 14C, 14D, 14F and the like are used as interconnections for a second circuit. The interconnections 12C, 12D and the like, for the first circuit, which radiate or dislike an electromagnetic noise are covered sufficiently with a conductive layer 16 for electromagnetic shielding use, and can effectively restrain the electromagnetic noise from coming in and out. First-layer interconnections 12E and 12F are connected to each other by the second-layer interconnection 14F; the first-layer interconnection 12D is formed so as to be extended to the lower part of the second-layer interconnection 14F. When such crossed interconnections are adopted, the first-layer and second-layer interconnections can be used easily in right places; most of interconnections for the first circuit can be formed as the first-layer interconnections and most of interconnections for the second circuit can be formed as the second-layer interconnections. As a result, the degree of freedom of interconnections is enhanced.

公开(公告)号：JPH04129428A

公开(公告)日：1992-04-30

申请号：JP25117490

申请日：1990-09-20

Applicant: YAMAHA CORP

Inventor： KADAKA TAKAYUKI ,  MOTOME MITSUHIRO ,  HIRANO MASAZO ,  HOSHI JURO ,  KISHII TATSUYA ,  MORITA KUNIAKI

IPC: H03M3/04

Abstract: PURPOSE:To reduce reflected noise based on a data noise mixed in a system clock by providing a filter eliminating noise at a transmission frequency of a digital input and its vicinity frequency to the D/A converter. CONSTITUTION:A filter 20 eliminating noise at a transmission frequency fs of a digital signal A and in its vicinity frequency and passing a system clock signal phis whose frequency fs is provided to an output of a clock generator 16 and the system clock signal phis passing through the filter 20 is fed to a digital filter 10, a noise shaper 12 and a waveform shaping circuit 14. Thus, waveform shaping is implemented based on the system clock signal phis having almost no noise. Thus, reflected noise is not almost included in the waveform shaping output.

公开(公告)号：JPH04111537A

公开(公告)日：1992-04-13

申请号：JP22917990

申请日：1990-08-30

Applicant: YAMAHA CORP

Inventor： KADAKA TAKAYUKI ,  MOTOME MITSUHIRO ,  HIRANO MASAZO ,  HOSHI JURO ,  KISHII TATSUYA ,  MORITA KUNIAKI

IPC: H03M3/02 ,  H03M3/04

Abstract: PURPOSE:To improve S/N of the analog output based on a waveform shaped output by separating the power system of a waveform shaping part from that of a preceding stage circuit to prevent an influence of the noise in the power system of the preceding stage circuit upon the waveform shaped output. CONSTITUTION:In an oversampling type DA converter, the power system of the waveform shaping part of a waveform shaping circuit is separated from that of the circuit preceding the waveform shaping part. That is, two power lines of a NAND gate 22 are separated from a power line VDD1 of a first power system and GND1 and are connected to a power line VDD2 of a second power system and GND2. Consequently, the potential variance of power lines has not an influence upon the power system of the waveform shaping part though occurring in the preceding stage circuit, and the waveform shaped output of less noise is obtained. Thus, S/N of the analog output is improved.

公开(公告)号：JP2591286B2

公开(公告)日：1997-03-19

申请号：JP22917990

申请日：1990-08-30

Applicant: YAMAHA CORP

Inventor： KADAKA TAKAYUKI ,  MOTOME MITSUHIRO ,  HIRANO MASAZO ,  HOSHI JURO ,  KISHII TATSUYA ,  MORITA KUNIAKI

IPC: H03M3/02 ,  H03M3/04

公开(公告)号：JPH04179316A

公开(公告)日：1992-06-26

申请号：JP30790190

申请日：1990-11-14

Applicant: YAMAHA CORP

Inventor： KADAKA TAKAYUKI ,  MOTOME MITSUHIRO ,  HIRANO MASAZO ,  HOSHI JURO ,  KISHII TATSUYA ,  MORITA KUNIAKI

IPC: H03M3/04

Abstract: PURPOSE:To reduce loopback noise and to improve an S/N by cancelling a noninverted digital input and an inverted digital input coming suddenly to a clock generation means, and preventing the mixing of data noise with a system clock signal. CONSTITUTION:A second input signal line 24 is arranged in parallel to a first input signal line 20 guiding a digital input to a noise shaper 12 and an inversion means 22 inverting the digital input and transmitting it is provided. The inverted digital input from the inversion means 22 is supplied to the second input signal line 22. The noninverted digital input from the first input signal line 20 and the inverted digital input from the second input signal line 24 coming suddenly to the clock oscillation terminal of the clock generator. Since the phases of the inputs are opposite and sizes are almost equal, they cancel each other and power as noise comes to considerably small. Thus, the loopback nose is reduced and the S/N can be improved.

公开(公告)号：JPH04129427A

公开(公告)日：1992-04-30

申请号：JP25117390

申请日：1990-09-20

Applicant: YAMAHA CORP

Inventor： KADAKA TAKAYUKI ,  MOTOME MITSUHIRO ,  HIRANO MASAZO ,  HOSHI JURO ,  KISHII TATSUYA ,  MORITA KUNIAKI

IPC: H03M3/04

Abstract: PURPOSE:To reduce reflected noise based on a data noise mixed in a system clock by deciding a transmission frequency of a digital input so as to be equal to an integral number of multiple of the system clock number of a noise shaper or its vicinity. CONSTITUTION:A transmission frequency fs to a noise shaper 12 is decided to be equal to a multiple of (n) of the frequency fs of a system clock signal phis or its vicinity, where (n) is a positive integer. Thus, let (n) be 1, mixed noise in the system clock is caused at the frequency fs in which noise power is minimum and in the vicinity. Thus, reflected noise is minimized.