公开(公告)号：HK1059991A1

公开(公告)日：2004-07-23

申请号：HK04102733

申请日：2004-04-19

Applicant: YAMAHA CORP

Inventor： KISHII TATSUYA

IPC: H03G20060101 ,  H03G3/02 ,  H03G5/10

公开(公告)号：JP2011066743A

公开(公告)日：2011-03-31

申请号：JP2009216628

申请日：2009-09-18

Applicant: Yamaha Corp ,  ヤマハ株式会社

Inventor： NAKAMURA KATSUYOSHI ,  KISHII TATSUYA ,  MIYAZAKI MASAHITO ,  TSUCHIYA HIROTOSHI ,  MAKINO KEN

IPC: H03F1/02 ,  H03F3/21

Abstract: PROBLEM TO BE SOLVED: To provide a power amplifier circuit which can constantly and stably switch power supply voltage in suitable timing so that a clip may not be generated in output signal waveform.
SOLUTION: A load driving section 1 has: a differential amplifier 10 which generates an output signal AMPO for driving a load to be given to an output terminal 102; a voltage dividing circuit 11 which divides voltage between an input terminal 101 and the output terminal 102 by resistors R1a and R2a to be given to a reversed-phase input terminal of the differential amplifier 10; and a voltage dividing circuit 12 which makes a signal obtained by dividing voltage between the input signal AMPO of the input terminal 101 and a reference level by resistors R1b and R2b into a reversed phase to be given to a positive phase input terminal of the differential amplifier 10. A power control circuit 2 switches power supply voltages VDD and VSS to be supplied to the differential amplifier 10 from power supply voltage ±V1 to larger power supply voltage ±V2 when amplitude of a signal Vp to be given to the positive phase input terminal of the differential amplifier 10 exceeds a threshold.
COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 要解决的问题：提供一种功率放大器电路，其可以在适当的定时恒定地稳定地切换电源电压，从而在输出信号波形中不会产生一个夹子。 解决方案：负载驱动部分1具有：差分放大器10，其产生用于驱动要提供给输出端子102的负载的输出信号AMP0; 分压电路11，通过电阻器R1a和R2a将输入端子101和输出端子102之间的电压分压到差分放大器10的反相输入端子; 以及分压电路12，其将通过将输入端子101的输入信号AMP0之间的电压和电阻器R1b和R2b的参考电平分压而获得的信号反相提供给差分放大器的正相输入端子 电源控制电路2将要提供给差分放大器10的电源电压VDD和VSS从供电电压±V1切换到较大的电源电压±V2，当向正相输入端子提供信号Vp的幅度时 差分放大器10超过阈值。 版权所有（C）2011，JPO＆INPIT

公开(公告)号：JP2011066735A

公开(公告)日：2011-03-31

申请号：JP2009216520

申请日：2009-09-18

Applicant: Yamaha Corp ,  ヤマハ株式会社

Inventor： KISHII TATSUYA ,  MIYAZAKI MASAHITO ,  NAKAMURA KATSUYOSHI ,  MAKINO KEN

IPC: H03F1/00 ,  H03F3/20 ,  H03F3/68

Abstract: PROBLEM TO BE SOLVED: To reduce pop noise of an audio amplifier, which amplifies an audio signal received from a sound source by amplifiers of a plurality of stages in order and outputs the resulting signal, without providing an offset cancel circuit on all of the plurality of amplifiers.
SOLUTION: In the audio amplifier including a preamplifier serving as an electronic variable resistor and a power amplifier which amplifies the signal level of the audio signal amplified by the preamplifier up to a signal level suitable for speaker driving and outputs the audio signal, only the power amplifier is provided with the offset cancel circuit. When the audio amplifier is activated, the offset cancel circuit is placed in operation first in a state where the preamplifier is muted, and thereafter, the preamplifier is made to perform processing for amplifying and outputting the audio signal supplied from the sound source while the amplification factor is increased with time from a minimum value up to a value corresponding to reproduced sound volume set by a user.
COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 要解决的问题：为了减少音频放大器的弹奏噪声，音频放大器根据多个级的放大器依次放大从声源接收的音频信号，并输出结果信号，而不提供所有的偏移消除电路 的多个放大器。 解决方案：在包括用作电子可变电阻器的前置放大器的音频放大器和放大由前置放大器放大的音频信号的信号电平达到适于扬声器驱动的信号电平的功率放大器并输出音频信号的情况下， 仅功率放大器设置有偏移消除电路。 当音频放大器被激活时，偏移消除电路首先在前置放大器被静音的状态下运行，此后，使前置放大器执行用于放大和输出从声源提供的音频信号的处理，同时放大 因子随着时间从最小值增加到对应于用户设置的再现音量的值。 版权所有（C）2011，JPO＆INPIT

公开(公告)号：JPH07240690A

公开(公告)日：1995-09-12

申请号：JP5451394

申请日：1994-02-28

Applicant: YAMAHA CORP

Inventor： KISHII TATSUYA ,  YAMADA YASUO

IPC: H03M1/74 ,  H03K17/693

Abstract: PURPOSE:To provide a D/A converter circuit obtaining an excellent output current characteristic without increasing chip size. CONSTITUTION:Each source of plural current source PMOS transistors (TRs) Q21 is connected to a VDD line 13, and plural reference voltage source PMOS TRs Q23 providing a constant voltage through diode connection to a gate-source of each of the current source PMOS TRs Q21 as a gate-source voltage are arranged adjacent the one or plural current source PMOS TRs Q21. A switching PMOS TR Q22 is connected in series with each current source PMOS TRs Q21, turned on/off with each of bit data being digital data to lead a current to an output terminal. Each of bit data IN is used to drive the switching MOS TR Q22 via a CMOS inverter 11.

公开(公告)号：JPH05206812A

公开(公告)日：1993-08-13

申请号：JP33909991

申请日：1991-12-20

Applicant: YAMAHA CORP

Inventor： KISHII TATSUYA

IPC: H03K17/22

Abstract: PURPOSE:To surely supply a set/reset signal without using the resistor or the external type capacitor by connecting a control terminal and a first terminal to each other, and turning on a switching element when potential difference is over a prescribed value. CONSTITUTION:An NchTr 10 is an n-channel type MOS transistor with threshold voltage Vr, and when the potential difference between its gate and source becomes over the threshold voltage Vr, its drain and source are turned into an ON-state. Then, in each NchTr 101 to 103, the drain and gate are connected to each other and further, the neighboring sources and drains are connected to each other. Besides, voltage VDD is impressed to the drain of the NchTr 101, and the source of the NchTr 103 is connected to the ground. Thus, since when sufficient time elapses after the time of the charge of power supply, all the NchTrs 101 to 103 are turned on, terminal voltage at that time becomes the voltage V voltage-divided by the on-resistance of the NchTr 101 and the resultant on-resistance of the NchTrs 102 and 103, and the reset signal can be supplied.

公开(公告)号：JPH0547767A

公开(公告)日：1993-02-26

申请号：JP23088691

申请日：1991-08-19

Applicant: YAMAHA CORP

Inventor： KISHII TATSUYA

IPC: H01L23/52 ,  H01L21/3205 ,  H01L23/14 ,  H01L23/552

Abstract: PURPOSE:To prevent electromagnetic wave noises from going in and out of an integrated circuit device by employing a proper wiring structure. CONSTITUTION:Conductive layers such as a polycrystalline Si layer 14 and a metal layer 22 are formed above and beneath a wiring layer 18 along its longitudinal direction and conductors such as metal layers 18a and 18b are formed on the left side and the right side of the wiring layer 18 along its longitudinal direction by a multilayer interconnection technology. These conductive layers and conductors are connected to each other and connected to a grounding terminal to construct an electromagnetic shield. The electromagnetic shield effectively suppresses electromagnetic wave noises which are emitted by the wiring layer 18 to jump into the other circuit parts and are emitted by the other circuit parts to jump into the wiring layer 18, so that the degree of freedom for layout can be improved.

公开(公告)号：JPH04150418A

公开(公告)日：1992-05-22

申请号：JP27359790

申请日：1990-10-12

Applicant: YAMAHA CORP

Inventor： KADAKA TAKAYUKI ,  MOTOME MITSUHIRO ,  HIRANO MASAZO ,  KISHII TATSUYA ,  MORITA KUNIAKI ,  HOSHI JURO

IPC: H03M3/04 ,  H03H17/00 ,  H03H17/02 ,  H03M3/02 ,  H03M7/00

Abstract: PURPOSE:To obtain a low-noise analog output by frequency-dividing a system clock signal having a frequency fs into

公开(公告)号：JPH04115713A

公开(公告)日：1992-04-16

申请号：JP23519390

申请日：1990-09-05

Applicant: YAMAHA CORP

Inventor： KADAKA TAKAYUKI ,  MOTOME MITSUHIRO ,  HIRANO MASAZO ,  KISHII TATSUYA ,  MORITA KUNIAKI ,  HOSHI JURO

IPC: H03M1/10 ,  H03K5/00

Abstract: PURPOSE:To obtain a pulse output with much less noise by interposing 2nd and 3rd transistors(TRs) turned on in response to a synchronizing pulse with a narrower pulse width than that of a data pulse in series between an output terminal and a 1st TR turned on in response to the data pulse. CONSTITUTION:With a digital signal (P) set to '1', TR T1 is turned on and a TR T6 is turned off, a clock signal phib goes to '1' and then TRs T2, T3 are turned on and a TR T4 is turned off. Then the signals P, phib go both to '1', the TRs T1-T3 are all tuned on and an output Q goes to 0. In this case, the period when the output Q takes 0 depends on the pulse width of the signal phib. The noise attended with a level change is blocked by the TRs T2, T3 in the off state even when the signal (P) 12 (when the TRs T2, T3 are turned off and the TR T4 is turned on) signal phib and the noise does not appear at the output Q. Thus, a wave shaping output C with less noise is obtained.

公开(公告)号：JP2012010163A

公开(公告)日：2012-01-12

申请号：JP2010145209

申请日：2010-06-25

Applicant: Yamaha Corp ,  ヤマハ株式会社

Inventor： YOSHIOKA DAISUKE ,  HARUHANA HIDEYO ,  KISHII TATSUYA

IPC: H03K19/00 ,  H03F1/02 ,  H03K17/22 ,  H03K17/30

Abstract: PROBLEM TO BE SOLVED: To provide a mode control circuit which reduces power consumption of the mode control circuit switching modes in a semiconductor integrated circuit having a plurality of operation modes including a power down mode.SOLUTION: A voltage comparator 30A with an offset is provided as a circuit for determining whether to set or cancel a power-down based on a controlling voltage. While the controlling voltage VC is lower than a offset voltage V0 and the voltage comparator 30A with the offset turns a power-down cancellation signal MD0 to anti-active level, a reference voltage generation circuit 10A can not be operated, and reference voltages V1 to V3 for use in comparison with the controlling voltage VC cannot be output. When the controlling voltage VC rises beyond the offset voltage V0 and the power down cancellation signal MD0 turns to active level, the reference voltage generation circuit 10A operates and the mode switching is performed by comparing reference voltages V1 to V3 with the controlling voltage VC.

Abstract translation: 要解决的问题：提供一种模式控制电路，其减少具有包括断电模式的多种操作模式的半导体集成电路中的模式控制电路切换模式的功耗。 提供具有偏移的电压比较器30A作为用于基于控制电压确定是否设置或取消掉电的电路。 当控制电压VC低于偏移电压V0时，具有偏移的电压比较器30A使掉电消除信号MD0变为反激电平，因此不能操作基准电压产生电路10A，并且参考电压V1至 V3无法与控制电压VC进行比较。 当控制电压VC超过偏移电压V0并且掉电消除信号MD0变为有效电平时，参考电压产生电路10A工作，并通过将参考电压V1至V3与控制电压VC进行比较来执行模式切换。 版权所有（C）2012，JPO＆INPIT

公开(公告)号：JP2011067038A

公开(公告)日：2011-03-31

申请号：JP2009216696

申请日：2009-09-18

Applicant: Yamaha Corp ,  ヤマハ株式会社

Inventor： MIYAZAKI MASAHITO ,  KAWAI HIROKATA ,  KISHII TATSUYA ,  NAKAMURA KATSUYOSHI ,  MAKINO KEN

IPC: H02M3/07 ,  H03F3/21

CPC classification number: H02M3/07

Abstract: PROBLEM TO BE SOLVED: To provide a charge pump for selecting two kinds of voltages, namely, a high voltage and a low voltage enabling generation, and smooth transition from an operation state which outputs the high voltage to an operation state which outputs the low voltage. SOLUTION: When a step-down command is given in a high-voltage output mode, transition to a relay mode is once performed. In the relay mode, since two kinds of operation, namely, a smoothing operation for separating an input power supply from first and second capacitors for output and a flying capacitor to connect the flying capacitor and the first capacitor for output in parallel, and a flying operation for separating the flying capacitor from the first capacitor for output and connecting to the second capacitor for output in parallel, are repeated, the charge voltage of each capacitor is lowered, while the voltage values are maintained to be equal. Then, transition to a low-voltage output mode is performed, after the charge voltage of the capacitor lowers is awaited. COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 要解决的问题：提供一种用于选择两种电压的电荷泵，即，能够产生高电压和低电压的电压，并且从输出高电压的操作状态到输出的操作状态的平滑过渡 低电压。

解决方案：当在高电压输出模式下给出降压命令时，一旦执行到继电器模式的转换。 在继电器模式中，由于两种操作，即用于将输入电源与用于输出的第一和第二电容器分离的平滑操作和用于连接飞行电容器的飞跨电容器和用于并联输出的第一电容器的两种操作，以及飞行 将飞秒电容器与用于输出的第一电容器分离并连接到并联输出的第二电容器的操作被重复，每个电容器的充电电压降低，同时将电压值保持相等。 然后，等待电容器的充电电压下降之后，转换到低电压输出模式。 版权所有（C）2011，JPO＆INPIT