公开(公告)号：JP2000293169A

公开(公告)日：2000-10-20

申请号：JP10445599

申请日：1999-04-12

Applicant: YAMAHA CORP

Inventor： HASEBE SEI ,  KAMIYA SATORU

IPC: G10H1/00 ,  G10H1/02 ,  G10H7/02

Abstract: PROBLEM TO BE SOLVED: To provide a musical sound generating device which can shorten the time needed to actually output a played sound after a user indicates the playing and can be manufactured at low cost. SOLUTION: This device is equipped with a hardware sound source 7 which has a storage part stored with waveform data representing a part of an attack part of a musical sound waveform and outputs waveform data (a) corresponding to a received MIDI event, a software sound source 11 (longer in the time from the reception of the MIDI event to the output of waveform data than the hardware sound source 7) which outputs waveform data (b) representing the whole musical sound waveform, and a waveform synthesis part 9 which cross-fades and outputs the waveform data outputted from the hardware sound source 7 and software sound source 10.

公开(公告)号：JPH1146400A

公开(公告)日：1999-02-16

申请号：JP20043997

申请日：1997-07-25

Applicant: YAMAHA CORP

Inventor： KAMIYA SATORU

IPC: H04S3/00 ,  G10K15/00 ,  H03G11/00 ,  H03H17/02 ,  H04S5/02 ,  H04S7/00

Abstract: PROBLEM TO BE SOLVED: To provide a sound image localization device by which a presence of as if a sound source were actually in existence there is obtained, based on position information of the sound source placed at other positions. SOLUTION: An audio signal S received by a sound image localization device 100 is separated into signals S1, S2, S3, S4 and they are respectively given to an FR filter 105, an FL filter 106, an RL filter 107 and an RR filter 108. On the other hand, position information of a sound source is given to a parameter generator 109. The parameter generator 109 generates a signal used by each filter for time-delay processing and a signal used by each filter for amplitude adjustment processing, based on the received position information and provides outputs of the signals to each filter. Each filter applies delay processing and amplitude adjustment to the received signal S, based on the signals generated by the parameter generator 109 and provides the outputs of signals S'1, S'2, S'3 and S'4.

公开(公告)号：JPH1078949A

公开(公告)日：1998-03-24

申请号：JP23209296

申请日：1996-09-02

Applicant: YAMAHA CORP

Inventor： KAMIYA SATORU

IPC: G06F9/28 ,  G06F17/10

Abstract: PROBLEM TO BE SOLVED: To provide a digital signal processor which excels in its flexibility and fast workability and can fast process the digital signal of optional contents. SOLUTION: An arithmetic array 1 consists of plural basic arithmetic units #0 to #15. A signal path forming part 2 forms the signal paths among the units #0 to #15 and also between these units and a memory part 3 based on a given program. Then the digital process of optional contents is processed by the array 1 where the signal paths are formed.

公开(公告)号：JPH08106383A

公开(公告)日：1996-04-23

申请号：JP26464094

申请日：1994-10-04

Applicant: YAMAHA CORP

Inventor： KAMIYA SATORU

IPC: G06F9/30 ,  C04B28/34

Abstract: PURPOSE: To select the optimum programming and processing modes and an optimum processing speed in response to the contents of processing to be executed. CONSTITUTION: A fast processing program described in a reduction instruction set and a slow processing program described in a fast function instruction set are stored in a main memory 1 centering on a speed switching instruction. When the speed switching instruction is carried out, the execution clocks ϕ' are switched and also the decoders 7 and 11 to which the instruction sets are supplied are switched. A multiplier 16 carries out an operation based on the pipeline processing while a fast program is carried out. Furthermore the multiplier 16 carries out an operation to directly fetch the data from the memory 1 while a slow program is carried out.

公开(公告)号：JPH0855034A

公开(公告)日：1996-02-27

申请号：JP20801394

申请日：1994-08-09

Applicant: YAMAHA CORP

Inventor： KAMIYA SATORU ,  SAITO AKITOSHI

IPC: G06F9/48 ,  G06F9/46

Abstract: PURPOSE:To reduce interruption overheads without complicating hardware configuration even when the number of tasks to be processed is increased. CONSTITUTION:This arithmetic processor 1 is provided with two sets of register groups 3 and 4 for storing a pointer, a status and the other data required for internal operations. When one of the register groups 3 or 4 is accessible from the inside (in use), the other register group 4 or 3 is accessible from the outside (unused) and the two sets of the register groups 3 and 4 are switched corresponding to switching signals SW from the outside. An external processor 2 is provided with a memory 6 for saving the contents of the register groups 3 and 4 in the inside, returns the contents of the register group stored in the memory 6 and required for the task to be activated next to the unused register group 3 or 4 at the time of an interruption processing, then, supplies the switching signals SW to the arithmetic processor 1 and switches the register groups 3 and 4. Then, the contents of the unused register group 4 or 3 after changeover are saved in the memory 6.

公开(公告)号：JPH0621851A

公开(公告)日：1994-01-28

申请号：JP19487292

申请日：1992-06-29

Applicant: YAMAHA CORP

Inventor： KAMIYA SATORU

IPC: H04B3/23

Abstract: PURPOSE:To save the capacity of a delay memory required for delay control when an echo component is eliminated. CONSTITUTION:Transmission data are divided into blocks in the unit of 3 bits by a transmission data block processing section 1 and the result is modulated by a 1st modulator 2. A 1st digital modulation signal outputted from the 1st modulator 2 is converted into an analog transmission signal by a D/A converter 3 and sent and fed to an echo canceller 4 as a near-end echo signal. The transmission data are delayed by a prescribed time at a delay memory 5 and modulated by a 2nd modulator 6 and fed to the echo canceller 4 as a remote-end echo signal. Since the delay control in the delay memory 5 is applied not to a signal after modulation but to the transmission data before modulation, the memory capacity is decreased. The reception signal is ADD-converted by an A/D converter 7 and the result is inputted to other terminal of an adder 8. The adder 8 eliminates an echo component from a digital reception signal. The digital reception signal outputted from the adder 8 is demodulated into reception data by a demodulator 9.

公开(公告)号：JP2001216418A

公开(公告)日：2001-08-10

申请号：JP2000028022

申请日：2000-02-04

Applicant: YAMAHA CORP

Inventor： KAMIYA SATORU

IPC: G11B20/10 ,  G06F21/10 ,  G06Q10/00 ,  G06Q30/06 ,  G06Q50/00 ,  G06Q50/10 ,  G10K15/02 ,  G11B19/04 ,  G06F17/60

Abstract: PROBLEM TO BE SOLVED: To effectively protect the copyright of music data. SOLUTION: Additional music data Dwav' synthesizing second compressed music data provided by compressing music data Dwav and enciphered additional data Dadd' are recorded on a new CD 21. This new CD 21 is sold through a sales shop 22 to a user. On the other hand, a decipher key KEY is sold by a second selling route through the Internet 23. The user, who acquires the decipher key KEY, deciphers the enciphered additional data Dadd', generates additional data Dadd and can utilize these data.

公开(公告)号：JP2001143395A

公开(公告)日：2001-05-25

申请号：JP32608099

申请日：1999-11-16

Applicant: YAMAHA CORP

Inventor： KAMIYA SATORU

IPC: G11B20/10 ,  G10L19/00 ,  H03M7/30

Abstract: PROBLEM TO BE SOLVED: To provide a data decoding device which can reproduce compressed digital sound data at a low cost for a long time. SOLUTION: This data decoding device 100 is equipped with a digital interface 106 for inputting compressed data reproduced by a CD player 200 which reproduces a CD 206 where digital data compressed in MP3 format are recorded, an MP3 decoder 108 which decodes the compressed data inputted by the digital interface 106 into uncompressed data, and a control circuit 105 which controls the reproducing speed of the compressed data by the CD player according to the data compression rate of the compressed data and controls the amount of the compressed data inputted to the MP3 decoder 108 through the digital interface 106.

公开(公告)号：JPH11282743A

公开(公告)日：1999-10-15

申请号：JP8580398

申请日：1998-03-31

Applicant: Yamaha Corp ,  ヤマハ株式会社

Inventor： KAMIYA SATORU

IPC: G06F12/02 ,  G06F12/00 ,  G06F12/10 ,  G06F13/28 ,  G10H7/02

CPC classification number: G06F12/1081

Abstract: PROBLEM TO BE SOLVED: To efficiently use a main memory by securing a continuous straight line area and a scattered area respectively on a main memory and appropriately use these areas.
SOLUTION: A hardware control driver 12 secures a continuous straight line area A1 and a scattered area A2 in a main memory 30, stores frequently used waveform data WT in the continuous straight line area A1 and stores less frequently used in the scattered area A2. In reading the waveform data WT stored in the scattered area A2, it is necessary to obtain a physical address P from a physical address acquisition/setting routine 13 each time a page end is detected by a page end detection circuit 220 but, in reading the waveform data WT stored in the continuous straight line area A1, it is not necessary to do so. Thus, it is possible to smoothly perform data transfer.
COPYRIGHT: (C)1999,JPO

Abstract translation: 要解决的问题：为了有效地使用主存储器，通过将连续的直线区域和散射区域分别固定在主存储器上并适当地使用这些区域。 解决方案：硬件控制驱动器12将连续直线区域A1和散射区域A2固定在主存储器30中，将频繁使用的波形数据WT存储在连续直线区域A1中，并且在散射区域A2中存储较少的频率。 在读取分散区域A2中存储的波形数据WT时，需要从页面结束检测电路220每次检测到页面结束时从物理地址获取/设置程序13获得物理地址P，但是在读取 存储在连续直线区域A1中的波形数据WT不需要这样做。 因此，可以平滑地进行数据传送。

公开(公告)号：JPH11163731A

公开(公告)日：1999-06-18

申请号：JP32639197

申请日：1997-11-27

Applicant: YAMAHA CORP

Inventor： NORO MASAO ,  SOGO AKIRA ,  KAMIYA SATORU

IPC: H03M1/18 ,  H03M3/02

Abstract: PROBLEM TO BE SOLVED: To extend the dynamic range of a ΔΣtype A/D converter, with a simple configuration. SOLUTION: A moving average calculation section 210 calculates a moving average of bit stream data D generated by a 1-bit A/D converter. Moving average data D' indicate a peak value of an input analog signal. A maximum value detection section 220 generates an attenuation control signal C1 by detecting a maximum value of the moving average data D' exceeding a first threshold level. Then the maximum value is stored in a maximum value latch register 230. A discrimination circuit 240 makes access to the maximum value latch register 230 and detects the maximum value being lower than second threshold consecutively for a prescribed time, then the circuit 240 generates an increase control signal C2.