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公开(公告)号：CA2313766A1
公开(公告)日：2001-01-13
申请号：CA2313766
申请日：2000-07-12
Applicant: YAMAHA CORP
Inventor： MUROI KUNIMASA , NORO MASAO , TODA KOJI , SOGO AKIRA
Abstract: An electro-coagulation printer uses an electrode control unit to drive electrodes (22) which are aligned in proximity to a rotation drum (24) having a conductive ink film on its surface. The electrodes are respectively electrified to partially coagulate the conductive ink film to form ink dots on the surface of the rotation drum, so that the ink dots are transferred onto a paper. Herein, the electrode control unit receives print data (3) from a hos t device (2) by way of an interface (4). Gradation data representing gradation values for one line of the electrodes are created based on the pri nt data and are output in a serial manner. The serial gradation data are converted to parallel data corresponding to the gradation values, which are held and controlled in output timing. That is, output timings of the gradation values are independently controlled based on correction information such that print positions of the ink dots are corrected in at least one of a paper-feed direction and an alignment direction of the electrodes. Based on the gradation values, pulse signals are generated to drive the electrodes respectively. Herein, each of the pulse signals consists of a number of pulses designated by the gradation value, or each of them consists of a single pulse whose pulse width depends on the gradation value. It is possible to differ the pulse signals from each other in phases. Thus, it is possible to print desired images on papers with a high quality and at a high speed.
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公开(公告)号：JP2000029498A
公开(公告)日：2000-01-28
申请号：JP20093598
申请日：1998-07-15
Applicant: YAMAHA CORP
Inventor： SOGO AKIRA
Abstract: PROBLEM TO BE SOLVED: To mix plural compressed digital audio signal with a small arithmetic processing quantity and with less signal deterioration. SOLUTION: Reading means 301 to 303 read the index parts of respective signal components formed by subjecting the various audio signals to band division out of a recording medium. Effective quantization region calculating means 311 to 313 and bit allocation determining means 321 to 323 determine the bit allocation of the virtual number parts of the respective signal components for every audio signal. The reading means 301 to 303 read out the virtual number parts by the same. Data reconstitution means 331 to 333 reconstitute the signal components of the original audio signals and a mixing means 340 executes the mixing thereof. An effective quantization region synthesizing means 350 and a bit allocation determining means 306 synthesize the effective quantization regions after the mixing and determines the bit allocation of the virtual number parts of the respective signal components. A quantizing means 370 quantizes the signal components according to the bit allocation.
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公开(公告)号：JPH08191217A
公开(公告)日：1996-07-23
申请号：JP1645395
申请日：1995-01-06
Applicant: YAMAHA CORP
Inventor： SOGO AKIRA
Abstract: PURPOSE: To output correct sine wave waveform data with high data accuracy in spite of lack in the resolution of addresses. CONSTITUTION: A ROM 1 stores sine wave data within a prescribed phase range and the lower five bits of seven-bit input phase data are accessed as address data. An order specifying circuit 2 specifies the forward and backward data reading order of address data in accordance with a phase area determined by the higher order two bits of the input phase data. A multiplier circuit 3 for adjusting the phase of reading data from the ROM 1 based upon the higher order two bits of the input phase data and sine wave/cosine wave specifying data S is connected to the output of the ROM 1. A compensating operation circuit 5 executes accuracy compensating operation for data read out from the ROM 1 by the use of data omitted at the time of address data conversion out of the input phase data.
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公开(公告)号：JPH0636477A
公开(公告)日：1994-02-10
申请号：JP21198092
申请日：1992-07-16
Applicant: YAMAHA CORP
Inventor： SOGO AKIRA , SAITO AKITOSHI
Abstract: PURPOSE:To prevent deterioration in regenerative data even when an unrestorable error occurs in digital data. CONSTITUTION:The digital data of one frame is constituted of bit allocation data and plural data allocated respectively by the bit allocation data. Plural data are constituted of characteristic part data allocated by bit number allocation data mantissa part data consisting of a bit number allocated by the bit number allocation data. When the error occurs in the bit allocation data, the digital data of one frame is unrestorable. In such a case, the output of a holding circuit 7 is selected by a selective circuit 6 and the characteristic part data are replaced by a former frame, and a noise generation circuit 9 is selected by the selective circuit 6 and the mantissa part data are replaced by noise data.
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公开(公告)号：JPH11163731A
公开(公告)日：1999-06-18
申请号：JP32639197
申请日：1997-11-27
Applicant: YAMAHA CORP
Inventor： NORO MASAO , SOGO AKIRA , KAMIYA SATORU
Abstract: PROBLEM TO BE SOLVED: To extend the dynamic range of a ΔΣtype A/D converter, with a simple configuration. SOLUTION: A moving average calculation section 210 calculates a moving average of bit stream data D generated by a 1-bit A/D converter. Moving average data D' indicate a peak value of an input analog signal. A maximum value detection section 220 generates an attenuation control signal C1 by detecting a maximum value of the moving average data D' exceeding a first threshold level. Then the maximum value is stored in a maximum value latch register 230. A discrimination circuit 240 makes access to the maximum value latch register 230 and detects the maximum value being lower than second threshold consecutively for a prescribed time, then the circuit 240 generates an increase control signal C2.
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Patent Agency Ranking
公开(公告)号：JPH08307276A
公开(公告)日：1996-11-22
申请号：JP13864095
申请日：1995-05-12
Applicant: YAMAHA CORP
Inventor： SOGO AKIRA
Abstract: PURPOSE: To provide the filter processing circuit used by a data system of a bit stream form in which a sampling rate of input data is used and desired filter processing is attained with a small circuit scale. CONSTITUTION: The filter processing circuit is used for a data signal system of 1-bit stream form, a digital filter 21 to apply desired filter processing to input data is a digital version of an analog filter configuring a switched capacitor circuit operated by a sampling rate of the input data in which an equation of charge mobile for each sampling period representing the input output characteristic is calculated digitally by the sampling rate. Multi-bit output data obtained by the digital filter 21 are converted again into 1-bit stream data by a ΣΔ modulator 22.
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公开(公告)号：JPH04277957A
公开(公告)日：1992-10-02
申请号：JP6395691
申请日：1991-03-05
Applicant: YAMAHA CORP
Inventor： SOGO AKIRA
IPC: H03D3/02 , H04L27/22 , H04L27/227
Abstract: PURPOSE:To respond to even a modulation signal of high frequency band with simple configuration by taking the weight mean by multiplying a PSK(phase shift keying)-modulated wave by a regenerative carrier and using a window function, and supplying it to a roll-off filter. CONSTITUTION:The PSK-mudulated wave and the regenerative carrier are A/D-converted by comparators 11, 15, and 19 as one-bit A/D conversion circuits, respectively. Pulse signals with pulse width equivalent to the phase difference between the PSK-modulated wave, the regenerative carrier and a signal in which the regenerative carrier is shifted by pi/2 are outputted from EXOR gates 12, 13 as multipliers, respectively. Weight averaging circuits 16, 20 which take the weight mean by using a prescribed window function as low-pass filters, and phase difference output from which a high frequency component is eliminated can be obtained. Such output receives band limitation based on the frequency characteristic of a set window function, therefore, the processing of the roll-off filters 17, 21 can be easily performed.
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公开(公告)号：JPH04150137A
公开(公告)日：1992-05-22
申请号：JP27152790
申请日：1990-10-08
Applicant: YAMAHA CORP
Inventor： SOGO AKIRA
Abstract: PURPOSE:To obtain a stable operation by using a filter so as to cut off only a frequency component of a push-button telephone signal in a message signal outputted from a message signal generating means and outputting the result to a line. CONSTITUTION:A filter 12 cuts off only a push-button telephone signal frequency component in a message signal outputted form a message signal generating means 11 and outputs the result to an output terminal T. Thus, even when a message signal is bypassed to a reception side as a side tone, since no push- button telephone signal frequency component is included in the side tone, a push-button telephone signal detection means 15 does not make mis-detection. Thus, a correct push-button telephone signal from a line is always detected to make a stable operation.
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公开(公告)号：JPS6432506A
公开(公告)日：1989-02-02
申请号：JP18801387
申请日：1987-07-28
Applicant: YAMAHA CORP
Inventor： SOGO AKIRA
Abstract: PURPOSE:To stabilize the circuit operation, to attain no adjustment and to obtain a digital demodulation output by providing an A/D conversion section converting an input FM modulation signal into a digital signal with a prescribed timing, a differentiation circuit and a decimation circuit. CONSTITUTION:An FM modulation signal inputted via a terminal 10 is given to an A/D converter 11 converting the signal into a digital signal synchronously with a sampling clock supplied via a terminal 12. A differentiation means 16 outputting a pulse synchronously with a clock signal every time the state of the output signal of the converter 11 changes and the decimation circuit 30 using a window function so as to weight said pulse and accumulating the pulses for a prescribed period to obtain a linear PCM signal subjected to FM demodulation are provided. Thus, the pulse width of an output pulse train from a pulse generating section 20 is made coincident with the pulse width of the clock signal, then no adjustment is required, the pulse width stability is improved and a linear PCM signal is obtained from the demodulation output.
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公开(公告)号：JPH10177471A
公开(公告)日：1998-06-30
申请号：JP33871296
申请日：1996-12-18
Applicant: YAMAHA CORP
Inventor： SOGO AKIRA
IPC: G06F7/00
Abstract: PROBLEM TO BE SOLVED: To start a new operation even in a situation where a new arithmetic result cannot be written by holding specified data within the arithmetic result of a multiplying and adding unit in an accumulator and outputting another kind of data to a transmission bus by bypassing the accumulator. SOLUTION: A delay element 20 which directly outputs the arithmetic result of the multiplying and adding unit 10 to a bus 302 is provided as a bypass means for the multiplying and adding block 100A of a 24-bit fixed point digital signal processor. The delay time of the delay element 20 is fixed so as to permit time delay from the input of data to registers A and B till an output to the bus 302 by way of the accumulators C and D to be equal to time delay from the input of data to the registers A and B till the output to the bus 302 by way of the delay element 20. Then, only data for executing return to ALU 12 so as to execute accumulation with a new multiplication result among the arithmetic results to be outputted from the multiplying and adding unit 10 is written in the accumulators C and D.
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