公开(公告)号：US09165790B2

公开(公告)日：2015-10-20

申请号：US13968409

申请日：2013-08-15

Applicant: Zhen Ding Technology Co., Ltd.

Inventor： Yong Ha Woo ,  E-Tung Chou ,  Wen-Lun Lo

IPC: H01L23/48 ,  H01L29/40 ,  H01L21/48 ,  H01L23/498

CPC classification number: H01L21/4853 ,  H01L23/49811 ,  H01L23/49894 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2924/15311 ,  H01L2924/00

Abstract: A packaging substrate includes a base layer, a first wiring layer, a second wiring layer, a first solder mask layer, a second solder mask layer and copper portions. The first second wiring layers are arranged on opposite sides of the base layer. The first solder mask layer covers the first wiring layer, and defines plenty of first openings. The first wiring layer exposed through the first openings serves as first contact pads. The second solder mask layer covers the second wiring layer. The second solder mask layer defines plenty of second openings. The second wiring layer exposed through the second openings serves as second contact pads. The copper portions are formed on the second contact pads. The copper portions protrude beyond the second solder mask layer. This disclosure further relates to a method of manufacturing the packaging substrate and a chip packaging body.

Abstract translation: 封装基板包括基底层，第一布线层，第二布线层，第一焊料掩模层，第二焊接掩模层和铜部分。 第一第二布线层布置在基层的相对侧上。 第一焊接掩模层覆盖第一布线层，并且限定了大量的第一开口。 通过第一开口露出的第一布线层用作第一接触垫。 第二焊料掩模层覆盖第二布线层。 第二焊接掩模层限定了大量的第二开口。 通过第二开口暴露的第二布线层用作第二接触垫。 铜部分形成在第二接触焊盘上。 铜部分突出超过第二焊接掩模层。 本公开还涉及制造封装基板和芯片封装体的方法。

公开(公告)号：US09173298B2

公开(公告)日：2015-10-27

申请号：US14097251

申请日：2013-12-05

Applicant: Zhen Ding Technology Co., Ltd.

Inventor： Yong Ha Woo ,  E-Tung Chou ,  Wen-Lun Lo

IPC: H01L21/48 ,  H01L21/44 ,  H05K3/00 ,  H01L23/498 ,  H01L25/10 ,  H05K3/34 ,  H05K3/40

CPC classification number: H01L25/105 ,  H01L21/4853 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49866 ,  H01L24/09 ,  H01L2224/08238 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/01028 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/15738 ,  H01L2924/181 ,  H05K1/09 ,  H05K1/115 ,  H05K3/0017 ,  H05K3/3436 ,  H05K3/4007 ,  H05K2201/0347 ,  H05K2201/0379 ,  H05K2201/09836 ,  H05K2201/10674 ,  H05K2203/0384 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A packaging substrate includes a circuit board, a number of first conductive posts, and a number of second conductive posts. The circuit board includes a first base and a first conductive pattern layer formed on a first surface of the first base. The first conductive posts extend from and are electrically connected to the first conductive pattern layer. The second conductive posts extend from and are electrically connected to the first conductive pattern layer. The height of each of the second conductive posts are larger than that of each of the first conductive posts.

Abstract translation: 封装基板包括电路板，多个第一导电柱和多个第二导电柱。 电路板包括形成在第一基底的第一表面上的第一基底和第一导电图案层。 第一导电柱从第一导电图案层延伸并电连接到第一导电图案层。 第二导电柱从第一导电图案层延伸并与之电连接。 每个第二导电柱的高度大于每个第一导电柱的高度。

公开(公告)号：US09362248B2

公开(公告)日：2016-06-07

申请号：US14331330

申请日：2014-07-15

Applicant: Zhen Ding Technology Co., Ltd.

Inventor： Yong Ha Woo ,  E-Tung Chou ,  Wen-Lun Lo

IPC: H01L21/00 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H05K1/18 ,  H05K3/00 ,  H05K3/46

CPC classification number: H01L24/24 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3121 ,  H01L24/19 ,  H01L24/32 ,  H01L24/73 ,  H01L24/82 ,  H01L24/92 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/24227 ,  H01L2224/24247 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/82039 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18162 ,  H05K1/185 ,  H05K3/0097 ,  H05K3/4682 ,  H05K2203/1536 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2924/00

Abstract: A coreless package structure and a method for manufacturing same includes the steps of providing a supporting substrate comprising an etching resist layer and a copper foil. A groove is defined in the copper foil and a plurality of contact pads are formed on the surface of the copper foil. A chip including a plurality of electrode pads is received in the groove and a packaging layer is formed on a side of the copper foil. An insulating layer and a conductive pattern layer are formed on the packaging layer in that order, the conductive pattern layer being electrically connected to the contact pads and the electrode pads by a plurality of conductive bumps. Finally, the etching resist layer and the copper foil are removed to obtain a coreless package structure.

Abstract translation: 无芯封装结构及其制造方法包括提供包括抗蚀剂层和铜箔的支撑基板的步骤。 在铜箔中限定有凹槽，并且在铜箔的表面上形成多个接触垫。 包含多个电极焊盘的芯片被容纳在槽中，并且在铜箔的一侧上形成封装层。 绝缘层和导电图案层依次形成在封装层上，导电图案层通过多个导电凸块与接触焊盘和电极焊盘电连接。 最后，除去抗蚀剂层和铜箔，得到无芯封装结构。