公开(公告)号：MX9503581A

公开(公告)日：1997-05-31

申请号：MX9503581

申请日：1995-08-21

Applicant: AT & T CORP

Inventor： DRAGONE CORRADO

IPC: G02F1/313 ,  G02B6/12 ,  G02B6/293 ,  G02B6/34 ,  G02F1/01 ,  G02F1/225 ,  H04Q11/00 ,  H01J03/00

Abstract: La presente invencion proporciona un aparato optico que incluye un primer dispositivo de asignacion de ruta de frecuencia que tiene al menos un puerto de entrada y P puertos de salida, en donde P >_ 2. También proporciona un segundo dispositivo de asignacion de ruta de frecuencia que tiene P puertos de entrada y al menos un puerto de salida. P trayectorias opticas conectan o acoplan el puerto de entrada del primer dispositivo de asignacion de ruta de frecuencia al puerto de salida del segundo dispositivo de asignacion de ruta de frecuencia (FIGURA 3).

公开(公告)号：MX9706436A

公开(公告)日：1998-07-31

申请号：MX9706436

申请日：1997-08-22

Applicant: SAINT GOBAIN VITRAGE

Inventor： RENAUD FIX ,  OLIVIER GUISELIN ,  YUN LIN XUC

IPC: B32B17/06 ,  B32B7/02 ,  B32B17/10 ,  C03C17/34 ,  C03C17/36 ,  G02F1/1334 ,  G02F1/1335 ,  G02F1/157 ,  H01J03/00

Abstract: La invencion tiene por objetivo un encristalado con sistema activo (14, 16), con propiedades opticas y/o energéticas variables, principalmente del tipo del sistema con transmision/absorcion luminosa (4), del tipo de sistema con difusion luminosa variable (16), o fotocromo. Este incluye igualmente al menos un medio de proteccion térmico frente al sistema activo y/o de ajuste del aspecto optico conferido por dicho sistema al encristalado, medio bajo la forma de al menos un revestimiento (6; 17) con propiedades de reflexion en el infrarrojo y/o en el ultravioleta y/o en el visible.

公开(公告)号：WO1998022968A1

公开(公告)日：1998-05-28

申请号：PCT/US1997017491

申请日：1997-09-29

Applicant: INTEL CORPORATION

Inventor： INTEL CORPORATION ,  CHO, Sung-Soo ,  BRYANT, Diane, M. ,  KARDACH, James, P. ,  DENG, Feng

IPC: H01J03/00

CPC classification number: G06F13/4081 ,  G06F1/1632 ,  Y02D10/14 ,  Y02D10/151

Abstract: Prior art quiet docking and undocking method used an interface that was located within notebook computer (10), thus adding to the cost, complexity, weight, and power consumption of the notebook computer (10). The present invention provides for an apparatus for quiet docking of a notebook computer (10) to a docking station (11), including interface circuitry located within the docking station. The interface detects when the notebook computer (10) has been inserted within the docking station (11), and correspondingly enables a switch such that a common system bus is coupled between the notebook computer (10) and docking station (11). The interface also generates events to allow a software routine to configure the notebook computer (10) and docking station (11) without prior user intervention. The interface also includes cicuitry to detect an undock request, and correspondingly undock the computer such that a transaction occurring on the system bus is not affected.

Abstract translation: 现有技术的安静对接和脱离方法使用位于笔记本计算机（10）内的接口，从而增加笔记本计算机（10）的成本，复杂性，重量和功率消耗。 本发明提供了一种用于将笔记本计算机（10）安静地对接到对接站（11）的装置，包括位于对接站内的接口电路。 接口检测笔记本电脑（10）何时插入对接站（11）内，并且相应地启用开关，使得公共系统总线耦合在笔记本计算机（10）和坞站（11）之间。 界面还生成事件，以允许软件程序配置笔记本电脑（10）和扩展坞（11），无需用户干预。 该接口还包括检测未停靠请求的缓存，并相应地将计算机取消停靠，使得系统总线上发生的事务不受影响。

公开(公告)号：WO1997031386A1

公开(公告)日：1997-08-28

申请号：PCT/US1997000850

申请日：1997-01-15

Applicant: IOMEGA CORPORATION

Inventor： IOMEGA CORPORATION ,  JOLLEY, David, Lee ,  BAKER, William, Paul ,  JOHNSON, Rick, L. ,  NEWMAN, Jon

IPC: H01J03/00

CPC classification number: G06F13/385 ,  G06F13/4068

Abstract: A multiple interface input/output port (11) allows communications between an interface bus (14) of a peripheral device (10) and any one of a plurality of different types of interface buses (18) that may be provided in a host computer (16). An interface bus detection circuit (22) detects which type of interface bus (18) the peripheral device (10) is connected to on the host computer (16), and communications are then routed through an appropriate interface adapter (26) that enables communication between the interface buses (18) of the peripheral device (10) and host computer (16). The interface bus detection circuit (22) compares signal levels on selected ones of the lines (45) of the interface bus (14) of the host computer (16) to a reference potential to determine which of the selected lines (45) are grounded. The circuit then identifies the type of the interface bus (18, 14) to which it is connected based on the determination of which of the selected lines (45) of the interface bus (14) are grounded.

Abstract translation: 多接口输入/输出端口（11）允许外围设备（10）的接口总线（14）与可以提供在主计算机中的多种不同类型的接口总线（18）中的任何一种之间的通信 16）。 接口总线检测电路（22）检测在主计算机（16）上连接外围设备（10）的接口总线（18）的类型，然后通过适当的接口适配器（26）将通信路由到能够进行通信 在外围设备（10）的接口总线（18）和主计算机（16）之间。 接口总线检测电路（22）将主计算机（16）的接口总线（14）的选定线路（45）上的信号电平与参考电位进行比较，以确定哪个选定线路（45）接地 。 然后，该电路基于确定接口总线（14）中的哪一行接地来确定其连接到的接口总线（18,14）的类型。

公开(公告)号：WO1997022987A1

公开(公告)日：1997-06-26

申请号：PCT/US1996019658

申请日：1996-12-11

Applicant: INTEL CORPORATION ,  GILLESPIE, Byron ,  GARBUS, Elliot ,  FUTRAL, William

Inventor： INTEL CORPORATION

IPC: H01J03/00

CPC classification number: G06F13/28

Abstract: Computer system (100) having host processor (102), DMA unit (104), host memory (106) and external memory (108) wherein DMA unit (104) controls transference of data between host memory (106) and external memory (108) based upon data transference parameters specified in chain descriptors created by host processor (102) and stored as data structures within host memory (106). Dynamic appending of chain descriptors is achieved by employing resume bit stored within register (10) of DMA unit (104). Host processor (102), upon creating new group of chain descriptors to be appended to previous group, updates link value within last chain descriptor for the previous group to point to the first chain descriptor of the new group and also sets the resume bit. DMA unit (104) reads chain descriptor parameters, including link values, they perform data transfer operation specified by the chain descriptor parameters. Upon completion of the transfer operation, DMA unit (104) examines the resume bit, and, if set, DMA unit (104) rereads the link value for the current chain descriptor.

Abstract translation: 具有主处理器（102），DMA单元（104），主机存储器（106）和外部存储器（108）的计算机系统（100），其中DMA单元（104）控制主机存储器（106）和外部存储器（108）之间的数据传输 ）基于由主处理器（102）创建并存储为主机存储器（106）内的数据结构的链描述符中指定的数据转移参数。 通过采用存储在DMA单元（104）的寄存器（10）内的恢复位来实现链描述符的动态附加。 主机处理器（102）在创建要附加到先前组的新组链描述符时，更新先前组的最后链描述符内的链接值以指向新组的第一链描述符，并且还设置恢复位。 DMA单元（104）读取链描述符参数，包括链接值，它们执行链描述符参数指定的数据传输操作。 在完成传送操作时，DMA单元（104）检查恢复位，并且如果被设置，DMA单元（104）重读当前链描述符的链接值。

公开(公告)号：WO1995034905A1

公开(公告)日：1995-12-21

申请号：PCT/US1995005965

申请日：1995-05-17

Applicant: INTEL CORPORATION

Inventor： INTEL CORPORATION ,  CHEN, Chengwu ,  GLEY, Michael, A.

IPC: H01J03/00

CPC classification number: G06F13/24

Abstract: The computer system includes a bus (28), a CPU (21) coupled to the bus (28), and a memory (22) coupled to the bus (28). A peripheral device (25) is coupled to the bus (28) for performing a predefined peripheral operation. A logic (24) is coupled to the bus (28) and the peripheral device (25) for causing the CPU (21) to be interrupted to control the peripheral device (25) when the logic (24) receives a request for the peripheral (25) operation. The logic (24) does not control the peripheral (25) operation. The request may be generated by a software program running on the CPU (21) or by the peripheral device (25). Although the CPU (21) is controlling the peripheral operation, the existing peripheral controller-based application software can still be used. A method for controlling the peripheral device (25) for the peripheral operation is also described.

Abstract translation: 计算机系统包括总线（28），耦合到总线（28）的CPU（21）和耦合到总线（28）的存储器（22）。 外围设备（25）耦合到总线（28），用于执行预定义的外围操作。 当逻辑（24）接收到外围设备的请求时，逻辑（24）耦合到总线（28）和外围设备（25），用于使CPU（21）被中断以控制外围设备（25） （25）操作。 逻辑（24）不控制外设（25）操作。 该请求可以由在CPU（21）上运行的软件程序或外围设备（25）生成。 虽然CPU（21）正在控制外设操作，但仍然可以使用现有的基于外设控制器的应用软件。 还描述了一种用于控制用于外围操作的外围设备（25）的方法。

公开(公告)号：EP0204541A3

公开(公告)日：1987-08-12

申请号：EP86304202

申请日：1986-06-03

Applicant: English Electric Valve Company Limited

Inventor： Maitland, Arthur ,  Menown, Hugh ,  Neale, Christopher Vince

IPC: H01S03/03 ,  H01J01/02 ,  H01J03/00

CPC classification number: H01J61/90 ,  H01S3/03 ,  H01S3/031

Abstract: Discharge tube apparatus includes an outer containing vessel 8 and a structure comprising five metal cylinders 10, 11, 12, 13 and 14 located coaxially within it. Each of the metal cylinders includes projecting spacers 15 on its outer surface which serve to space it from adjacent ones. Such a structure is thermally insulating and enables a large temperature difference to be maintained between the interior of the discharge tube and the outer containing vessel 8. In other embodiments (not shown), a plurality of structures are included disposed along the axis of the tube. Also dispenser segments for dispensing part of the amplifying medium of a metal vapour laser may be included and arranged to shield vulnerable surfaces in the tube from direct exposure to the discharge.

公开(公告)号：EP0048856A3

公开(公告)日：1982-06-23

申请号：EP81107145

申请日：1981-09-10

Applicant: Siemens Aktiengesellschaft

Inventor： Feuerbaum, Hans-Peter, Dipl.-Phys. ,  Weyl, Reinhard, Dr.

IPC: H01J03/00 ,  H01J37/04

CPC classification number: H01J37/045

Abstract: Eine Elektrode (5) zur Strahlaustastung, die einfach zu bedienen ist, zuverlässig ist und kurze Pulse ermöglicht, wird auf einer annähernden Äquipotentialfläche angeord net, wobei diese annähernde Äquipotentialfläche im Durch laßbetrieb nahe dem Kathodenpotential liegt.

Abstract translation: 易于操作的光束消隐电极（5）是可靠的，并且允许在大致等电位表面上布置短脉冲，该近似等电位面在透射模式中大致处于阴极电位。

公开(公告)号：EP0027037A3

公开(公告)日：1981-04-22

申请号：EP80303480

申请日：1980-10-02

Applicant: Hitachi, Ltd.

Inventor： Maruyama, Masanori ,  Mizushima, Masashi ,  Fukushima, Masakazu ,  Miyamoto, Satoru ,  Sakai, Hideyuki

IPC: H01J03/00 ,  H01J29/56

CPC classification number: H01J29/566 ,  H01J29/46

Abstract: A television camera tube with electrostatic focusing and magnetic deflection comprises in an cylindrical envelope (1) a beam current control section, a main lens section and a sixth grid in the form of a mesh electrode. The beam current control section includes a cathode (4), a first grid (5) and a second grid (6) with an electron beam limiting diaphragm (7) disposed in this order. The main lens section includes third, fourth and fifth grids (8, 9, 10) in the form of cylindrical electrodes disposed in this order. Around the cylindrical envelope is mounted a magnetic deflection coil (12) whose length (ℓ D ) along the envelope axis is 0.18 to 0.40 times the distance (L) from the beam limiting diaphragm (7) tho the mesh electrode (11).

Abstract translation: 具有静电聚焦和磁偏转的电视摄像机管包括圆柱形外壳，光束电流控制，主透镜部分和网状电极形式的第六格栅。 光束电流控制部分依次包括阴极，第一栅极和具有电子束限制膜片的第二栅极。 主透镜部分包括依次布置的圆柱形电极形式的第三，第四和第五格栅。 在圆柱形外壳周围安装有磁偏转线圈，其沿着包络线的长度是从光束限制膜片到网状电极的距离的0.18至0.40倍。