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    Method for creating narrow trenches in dielectric materials
    3.
    发明授权
    Method for creating narrow trenches in dielectric materials 有权
    在介电材料中形成窄沟槽的方法

    公开(公告)号：US07560357B2

    公开(公告)日：2009-07-14

    申请号：US11532190

    申请日：2006-09-15

    Applicant: Gerald Beyer

    Inventor： Gerald Beyer

    IPC: H01L21/8238 ,  H01L21/336 ,  H01L21/76 ,  H01L29/76 ,  H01L29/00

    CPC classification number: H01L21/31111 ,  B81C1/00595 ,  B81C2201/0132 ,  B81C2201/0133 ,  H01L21/31633 ,  H01L21/76224 ,  H01L21/76816

    Abstract: A method for producing narrow trenches in semiconductor devices. The narrow trenches are formed by chemically changing the properties of a first dielectric layer locally, such that the side walls of a patterned hole in the first dielectric layer is converted locally and becomes etchable by a first etching substance. Subsequently a second dielectric material is deposited in the patterned structure and the damaged part of the first dielectric material is removed such that small trenches are obtained.

    Abstract translation: 一种在半导体器件中制造窄沟槽的方法。 通过局部化学地改变第一电介质层的性质来形成窄沟槽，使得第一介电层中的图案化孔的侧壁被局部地转换并且可被第一蚀刻物质蚀刻。 随后，在图案化结构中沉积第二介电材料，并且去除第一介电材料的损坏部分，从而获得小的沟槽。

    Methods for selective integration of airgaps and devices made by such methods
    4.
    发明授权
    Methods for selective integration of airgaps and devices made by such methods 有权
    通过这种方法制造的气囊和装置的选择性集成方法

    公开(公告)号：US07319274B2

    公开(公告)日：2008-01-15

    申请号：US11387188

    申请日：2006-03-22

    Applicant: Gerald Beyer ,  Jean Paul Gueneau de Mussy ,  Karen Maex ,  Victor Sutcliffe

    Inventor： Gerald Beyer ,  Jean Paul Gueneau de Mussy ,  Karen Maex ,  Victor Sutcliffe

    IPC: H01L23/48

    CPC classification number: H01L21/76802 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31633 ,  H01L21/764 ,  H01L21/76807 ,  H01L21/7682 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76831 ,  H01L21/76835 ,  H01L21/76877 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Methods for the production of airgaps in semiconductor devices and devices produced using such methods are disclosed. An example semiconductor device includes a damascene stack formed using such methods. The damascene stack includes a patterned dielectric layer including an interconnect structure, where the dielectric layer is formed of a dielectric material including Si, C and O. The damascene stack also includes a converted portion of the dielectric layer, where the converted portion is adjacent to the at least one interconnect structure and has a lower carbon content than the dielectric material. The damascene stack also includes an airgap formed adjacent to the interconnect structure, the airgap being formed by removing at least part of the converted portion using an etch compound.

    Abstract translation: 公开了使用这种方法生产半导体器件和器件中的气隙的方法。 示例性的半导体器件包括使用这种方法形成的镶嵌叠层。 镶嵌层包括包括互连结构的图案化电介质层，其中电介质层由包括Si，C和O的电介质材料形成。镶嵌层还包括电介质层的转换部分，其中转换部分与 所述至少一个互连结构并且具有比所述电介质材料低的碳含量。 镶嵌叠层还包括邻近互连结构形成的气隙，气隙通过使用蚀刻化合物去除至少部分转化部分而形成。

    METHOD FOR CREATING NARROW TRENCHES IN DIELECTRIC MATERIALS
    6.
    发明申请
    METHOD FOR CREATING NARROW TRENCHES IN DIELECTRIC MATERIALS 有权
    在电介质材料中形成窄轨的方法

    公开(公告)号：US20070066028A1

    公开(公告)日：2007-03-22

    申请号：US11532190

    申请日：2006-09-15

    Applicant: Gerald Beyer

    Inventor： Gerald Beyer

    IPC: H01L21/76

    CPC classification number: H01L21/31111 ,  B81C1/00595 ,  B81C2201/0132 ,  B81C2201/0133 ,  H01L21/31633 ,  H01L21/76224 ,  H01L21/76816

    Abstract: A method for producing narrow trenches in semiconductor devices. The narrow trenches are formed by chemically changing the properties of a first dielectric layer locally, such that the side walls of a patterned hole in the first dielectric layer is converted locally and becomes etchable by a first etching substance. Subsequently a second dielectric material is deposited in the patterned structure and the damaged part of the first dielectric material is removed such that small trenches are obtained.

    Abstract translation: 一种在半导体器件中制造窄沟槽的方法。 通过局部化学地改变第一电介质层的性质来形成窄沟槽，使得第一介电层中的图案化孔的侧壁被局部地转换并且可被第一蚀刻物质蚀刻。 随后，在图案化结构中沉积第二介电材料，并且去除第一介电材料的损坏部分，从而获得小的沟槽。

    Methods for selective integration of airgaps and devices made by such methods
    7.
    发明授权
    Methods for selective integration of airgaps and devices made by such methods 失效
    通过这种方法制造的气囊和装置的选择性集成方法

    公开(公告)号：US07078352B2

    公开(公告)日：2006-07-18

    申请号：US10957514

    申请日：2004-09-30

    Applicant: Gerald Beyer ,  Jean Paul Gueneau de Mussy ,  Karen Maex ,  Victor Sutcliffe

    Inventor： Gerald Beyer ,  Jean Paul Gueneau de Mussy ,  Karen Maex ,  Victor Sutcliffe

    IPC: H01L21/302

    CPC classification number: H01L21/76802 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31633 ,  H01L21/764 ,  H01L21/76807 ,  H01L21/7682 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76831 ,  H01L21/76835 ,  H01L21/76877 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A method for the production of airgaps in a semiconductor device and device produced therefrom. The formation of airgaps is accomplished, in part, by chemically and/or mechanically changing the properties of a first dielectric layer locally, such that at least part of said first dielectric layer is converted locally and becomes etchable by a first etching substance. The local conversion of the dielectric material may be achieved during anisotropic etching of the material in oxygen containing plasma or ex-situ by performing an oxidizing step (e.g., a UV/ozone treatment or supercritical carbon dioxide with addition of an oxidizer). Formation of airgaps is achieved after creation of conductive lines and, alternatively, a barrier layer by a first etching substance. The airgaps are formed in a dual damascene structure, near the vias and/or the trenches of the damascene structure.

    Abstract translation: 一种用于生产半导体器件中的气隙的方法及其制造的装置。 气隙的形成部分地通过局部地化学和/或机械地改变第一介电层的性质来实现，使得至少部分所述第一电介质层被局部转化并且可被第一蚀刻物质蚀刻。 电介质材料的局部转化可以在含氧等离子体中的材料的各向异性蚀刻期间进行，或者通过进行氧化步骤（例如，加入氧化剂的UV /臭氧处理或超临界二氧化碳）来实现。 在创建导电线之后实现气隙的形成，或者通过第一蚀刻物质形成阻挡层。 空气隙形成在双镶嵌结构中，靠近镶嵌结构的通孔和/或沟槽。

    Method of filling an opening in an insulating layer
    8.
    发明授权
    Method of filling an opening in an insulating layer 失效
    在绝缘层中填充开口的方法

    公开(公告)号：US06245653B1

    公开(公告)日：2001-06-12

    申请号：US09275922

    申请日：1999-03-24

    Applicant: Gerald Beyer ,  Karen Maex ,  Joris Proost

    Inventor： Gerald Beyer ,  Karen Maex ,  Joris Proost

    IPC: H01L2144

    CPC classification number: H01L21/76876 ,  H01L21/76843 ,  H01L21/76858 ,  H01L21/76877

    Abstract: The present invention is about a method for filling an opening in an insulating layer in a fast and highly reliable way and can be used to fill openings such as trenches and via holes simultaneously. This method is based on the principle of reaction enhanced wetting and simultaneous seed layer formation. The idea is, in contrast to trying to avoid the TiAl3 formation, to use this reaction to its advantage for the creation of an ultra-thin continuous Al-containing seed layer. The latter allows a bottom to top fill during the subsequent Al-containing metal deposition. As a consequence, the filling process proceeds much faster and is production worthy.

    Abstract translation: 本发明涉及一种用于以快速且高可靠的方式填充绝缘层中的开口的方法，并且可以同时填充诸如沟槽和通孔的开口。 该方法是基于反应增强润湿和同时种子层形成的原理。 这个想法是与试图避免TiAl3形成相反，将该反应用于产生超薄连续含Al种子层的优点。 后者允许在随后的含Al金属沉积期间从底部到顶部填充。 因此，填充过程进行得更快，生产价值。

    Methods for selective integration of airgaps and devices made by such methods
    10.
    发明申请
    Methods for selective integration of airgaps and devices made by such methods 审中-公开
    通过这种方法制造的气囊和装置的选择性集成方法

    公开(公告)号：US20060160353A1

    公开(公告)日：2006-07-20

    申请号：US11378116

    申请日：2006-03-16

    Applicant: Jean Gueneau de Mussy ,  Gerald Beyer ,  Karen Maex

    Inventor： Jean Gueneau de Mussy ,  Gerald Beyer ,  Karen Maex

    IPC: H01L21/4763 ,  H01L21/302

    CPC classification number: H01L21/76831 ,  H01L21/7682 ,  H01L23/5222 ,  H01L23/53238 ,  H01L23/53276 ,  H01L23/5328 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

    Abstract: Damascene stacks for use in semiconductor devices and methods for making such stacks are disclosed. An example damascene stack includes a substantially planar lower liner layer and a patterned sacrificial dielectric layer disposed on top of the lower liner layer, where the patterned sacrificial dielectric layer includes an interconnect structure of the damascene stack. The example damascene stack further includes a substantially planar upper liner layer disposed on top of the patterned sacrificial dielectric layer, where the upper liner layer being formed of a material that is resistant to etching by a first etch compound. There is at least one plug-hole in the upper liner layer, where the at least one plug-hole is (i) adjacent to the interconnect structure and (ii) formed by locally converting a portion of the upper liner layer to be etchable by the first etch compound and removing the locally converted portion of the upper liner layer using the first etch compound. The example damascene stack still further includes at least one air gap formed by removing at least a portion of the sacrificial dielectric layer through the at least one plug-hole in said upper liner layer.

    Abstract translation: 公开了用于半导体器件的大马士革叠层和用于制造这种叠层的方法。 示例镶嵌层包括基本平坦的下衬垫层和设置在下衬层的顶部上的图案化牺牲绝缘层，其中图案化牺牲电介质层包括镶嵌层的互连结构。 示例性镶嵌层还包括设置在图案化的牺牲介电层的顶部上的基本平坦的上衬层，其中上衬层由耐受第一蚀刻化合物的蚀刻的材料形成。 在上衬垫层中存在至少一个插塞孔，其中至少一个插塞孔为（i）与互连结构相邻，以及（ii）通过局部地将上衬垫层的一部分局部转换为可蚀刻的 第一蚀刻化合物，并使用第一蚀刻化合物去除上衬层的局部转化部分。 示例性镶嵌层还包括至少一个气隙，其通过去除所述上衬垫层中的至少一个塞孔而去除至少一部分牺牲介电层而形成。

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