中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

77 records (took 0.019 seconds)

    System, apparatus and method for providing hardware state feedback to an operating system in a heterogeneous processor
    1.
    发明授权
    System, apparatus and method for providing hardware state feedback to an operating system in a heterogeneous processor 有权

    公开(公告)号：US12182618B2

    公开(公告)日：2024-12-31

    申请号：US18322636

    申请日：2023-05-24

    Applicant: Intel Corporation

    Inventor： Praveen Kumar Gupta ,  Avinash N. Ananthakrishnan ,  Eugene Gorbatov ,  Stephen H. Gunther

    IPC: G06F9/48 ,  G06F1/08 ,  G06F1/10 ,  G06F1/3296 ,  G06F1/324

    Abstract: In one embodiment, a processor includes a power controller having a resource allocation circuit. The resource allocation circuit may: receive a power budget for a first core and at least one second core and scale the power budget based at least in part on at least one energy performance preference value to determine a scaled power budget; determine a first maximum operating point for the first core and a second maximum operating point for the at least one second core based at least in part on the scaled power budget; determine a first efficiency value for the first core based at least in part on the first maximum operating point for the first core and a second efficiency value for the at least one second core based at least in part on the second maximum operating point for the at least one second core; and report a hardware state change to an operating system scheduler based on the first efficiency value and the second efficiency value. Other embodiments are described and claimed.

    Method, apparatus and system for configuring a protocol stack of an integrated circuit chip
    3.
    发明授权
    Method, apparatus and system for configuring a protocol stack of an integrated circuit chip 有权

    公开(公告)号：US10282341B2

    公开(公告)日：2019-05-07

    申请号：US15671900

    申请日：2017-08-08

    Applicant: Intel Corporation

    Inventor： Bryan L. Spry ,  Marcus W. Song ,  Deepak M. Rangaraj ,  Avinash N. Ananthakrishnan ,  Robert J. Hayes ,  Aimee D. Wood ,  Adam E. Letendre ,  Brent R. Boswell

    IPC: G06F13/20 ,  G06F13/42 ,  G06F13/12

    Abstract: Techniques and mechanisms for configuring an integrated circuit (IC) chip to implement a protocol stack. In an embodiment, a transaction layer of the IC chip is operable to exchange with a link layer of the IC chip transaction layer packets (TLPs) having a format compatible with one defined in a Peripheral Component Interconnect Express™ (PCIe™) specification. Configuration circuitry of the IC chip provides for configuration of a first protocol stack including the transaction layer, circuitry of the link layer and a first physical layer of the IC chip. The configuration circuitry further provides for an alternative configuration of a second protocol stack including the transaction layer, circuitry of the link layer and a second physical layer of the IC chip. In another embodiment, the first protocol stack supports single-ended signaling to communicate TLP information, whereas the second protocol stack supports differential signaling to communicate TLP information.

    Multi-level loops for computer processor control
    4.
    发明授权
    Multi-level loops for computer processor control 有权

    公开(公告)号：US10216246B2

    公开(公告)日：2019-02-26

    申请号：US15281651

    申请日：2016-09-30

    Applicant: Intel Corporation

    Inventor： Doron Rajwan ,  Efraim Rotem ,  Eliezer Weissmann ,  Avinash N. Ananthakrishnan ,  Dorit Shapira

    IPC: G06F1/32 ,  G06F9/50 ,  G06F1/3228 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3237 ,  G06F17/50 ,  G06F1/3234 ,  G06F1/3293

    Abstract: In an embodiment, a processor includes processing cores, and a central control unit to: concurrently execute an outer control loop and an inner control loop, wherein the outer control loop is to monitor the processor as a whole, and wherein the inner control loop is to monitor a first processing core included in the processor; determine, based on the outer control loop, a first control action for the first processing core included in the processor; determine, based on the inner control loop, a second control action for the first processing core included in the processor; based on a comparison of the first control action and the second control action, select one of the first control action and the second control action as a selected control action; and apply the selected control action to the first processing core. Other embodiments are described and claimed.

Patent Agency Ranking