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    THERMAL BYPASS FOR STACKED DIES
    91.
    发明公开
    THERMAL BYPASS FOR STACKED DIES 审中-公开

    公开(公告)号：US20230154816A1

    公开(公告)日：2023-05-18

    申请号：US18055798

    申请日：2022-11-15

    Applicant: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.

    Inventor： Belgacem Haba ,  Christopher Aubuchon

    IPC: H01L23/36 ,  H01L23/00

    CPC classification number: H01L23/36 ,  H01L24/32 ,  H01L24/08 ,  H01L2224/32221 ,  H01L2224/08145

    Abstract: The disclosed technology relates to microelectronic devices that can dissipate heat efficiently. In some aspects, such a microelectronic device includes a first semiconductor element and at least one second semiconductor element disposed on the first semiconductor element. Such a microelectronic device may further include a thermal block disposed on the first semiconductor element and adjacent to the at least one second semiconductor element. The thermal block may include a conductive thermal pathway to transfer heat from the first semiconductor element to a heat sink disposed on the thermal block. In some embodiments, a coefficient of thermal expansion (CTE) of the thermal block is less than 10 μm/m° C. In some embodiments, a thermal conductivity of the thermal block is higher than 150 Wm-1K-1. at room temperature.

    DIFFUSION BARRIERS AND METHOD OF FORMING SAME
    92.
    发明申请
    DIFFUSION BARRIERS AND METHOD OF FORMING SAME 有权

    公开(公告)号：US20230132632A1

    公开(公告)日：2023-05-04

    申请号：US18050307

    申请日：2022-10-27

    Applicant: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.

    Inventor： Rajesh Katkar ,  Cyprian Emeka Uzoh

    IPC: H01L23/00

    Abstract: An element that is configured to bond to another element to define a bonded structure is disclosed. The element can include a dielectric bonding layer having a cavity that extends at least partially through a thickness of the dielectric bonding layer from a surface of the dielectric bonding layer. The element can also include a conductive feature that is at least partially disposed in the cavity. The conductive feature has a contact surface. The element can include a diffusion barrier layer between the conductive feature and a portion of the dielectric bonding layer. The barrier layer includes a barrier metal. The barrier metal of the diffusion barrier layer has an oxidation propensity that is greater than an oxidation propensity of the conductive feature.

    Heterogeneous annealing method
    93.
    发明授权
    Heterogeneous annealing method 有权

    公开(公告)号：US11631586B2

    公开(公告)日：2023-04-18

    申请号：US16914169

    申请日：2020-06-26

    Applicant: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.

    Inventor： Paul M. Enquist ,  Gaius Gillman Fountain

    IPC: H01L21/20 ,  H01L23/498 ,  H01L21/768 ,  H01L25/00 ,  H01L49/02 ,  H01L27/06 ,  H01L21/683 ,  H01L23/00 ,  H01L25/065

    Abstract: A method of integrating a first substrate having a first surface with a first insulating material and a first contact structure with a second substrate having a second surface with a second insulating material and a second contact structure. The first insulating material is directly bonded to the second insulating material. A portion of the first substrate is removed to leave a remaining portion. A third substrate having a coefficient of thermal expansion (CTE) substantially the same as a CTE of the first substrate is bonded to the remaining portion. The bonded substrates are heated to facilitate electrical contact between the first and second contact structures. The third substrate is removed after heating to provided a bonded structure with reliable electrical contacts.

    BONDED STRUCTURE WITH ACTIVE INTERPOSER
    94.
    发明申请
    BONDED STRUCTURE WITH ACTIVE INTERPOSER 有权

    公开(公告)号：US20230100032A1

    公开(公告)日：2023-03-30

    申请号：US17934514

    申请日：2022-09-22

    Applicant: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.

    Inventor： Belgacem Haba ,  Laura Wills Mirkarimi

    IPC: H01L23/538 ,  H01L23/48 ,  H01L23/00 ,  H01L25/065

    Abstract: A bonded structure is disclosed. The bonded structure can comprise a first semiconductor element having a first contact pad. An interposer can include a second contact pad on a first side of the interposer and a third contact pad and a fourth contact pad on a second side of the interposer opposite the first side, the second contact pad bonded to the first contact pad; a second semiconductor element having a fifth contact pad bonded to the third contact pad and a sixth contact pad bonded to the fourth contact pad. A switching circuitry can be configured to switch between a first electrical connection between the second and third contact pads and a second electrical connection between the second and fourth contact pads.

    Reliable hybrid bonded apparatus
    96.
    发明授权
    Reliable hybrid bonded apparatus 有权

    公开(公告)号：US12300661B2

    公开(公告)日：2025-05-13

    申请号：US18353019

    申请日：2023-07-14

    Applicant: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.

    Inventor： Cyprian Emeka Uzoh ,  Pawel Mrozek

    IPC: H01L23/48 ,  H01L23/00 ,  H01L23/52 ,  H01L29/40

    Abstract: Reliable hybrid bonded apparatuses are provided. An example process cleans nanoparticles from at least the smooth oxide top layer of a surface to be hybrid bonded after the surface has already been activated for the hybrid bonding. Conventionally, such an operation is discouraged. However, the example cleaning processes described herein increase the electrical reliability of microelectronic devices. Extraneous metal nanoparticles can enable undesirable current and signal leakage from finely spaced traces, especially at higher voltages with ultra-fine trace pitches. In the example process, the extraneous nanoparticles may be both physically removed and/or dissolved without detriment to the activated bonding surface.

    Integrated optical waveguides, direct-bonded waveguide interface joints, optical routing and interconnects
    99.
    发明授权
    Integrated optical waveguides, direct-bonded waveguide interface joints, optical routing and interconnects 有权

    公开(公告)号：US12271032B2

    公开(公告)日：2025-04-08

    申请号：US18508556

    申请日：2023-11-14

    Applicant: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.

    Inventor： Shaowu Huang ,  Javier A. Delacruz ,  Liang Wang ,  Guilian Gao

    IPC: G02B6/13 ,  G02B6/12

    Abstract: Integrated optical waveguides, direct-bonded waveguide interface joints, optical routing and interconnects are provided. An example optical interconnect joins first and second optical conduits. A first direct oxide bond at room temperature joins outer claddings of the two optical conduits and a second direct bond joins the inner light-transmitting cores of the two conduits at an annealing temperature. The two low-temperature bonds allow photonics to coexist in an integrated circuit or microelectronics package without conventional high-temperatures detrimental to microelectronics. Direct-bonded square, rectangular, polygonal, and noncircular optical interfaces provide better matching with rectangular waveguides and better performance. Direct oxide-bonding processes can be applied to create running waveguides, photonic wires, and optical routing in an integrated circuit package or in chip-to-chip optical communications without need for conventional optical couplers. An example wafer-level process fabricates running waveguides, optical routing, and direct-bonded optical interconnects for silicon photonics and optoelectronics packages when two wafers are joined.

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