公开(公告)号：US20190007334A1

公开(公告)日：2019-01-03

申请号：US15639641

申请日：2017-06-30

Applicant: INTEL CORPORATION

Inventor： Francesc Guim Bernat ,  Kshitij A. Doshi ,  Mark A. Schmisseur ,  Narayan Ranganathan ,  John Chun Kwok Leung

IPC: H04L12/911 ,  G06F13/40 ,  G06F9/455 ,  H04L12/40

Abstract: A host fabric interface (HFI) apparatus, including: an HFI to communicatively couple to a fabric; and a remote hardware acceleration (RHA) engine to: query an orchestrator via the fabric to identify a remote resource having an accelerator; and send a remote accelerator request to the remote resource via the fabric.

公开(公告)号：US20190004954A1

公开(公告)日：2019-01-03

申请号：US15640283

申请日：2017-06-30

Applicant: Intel Corporation

Inventor： Karthik Kumar ,  Thomas Willhalm ,  Patrick Lu ,  Francesc Guim Bernat ,  Shrikant M. Shah

IPC: G06F12/0862 ,  G06F12/02

Abstract: Devices and systems having memory-side adaptive prefetch decision-making, including associated methods, are disclosed and described. Adaptive information can be provided to memory-side controller and prefetch components that allow such memory-side components to prefetch data in a manner that is adaptive with respect to a particular read memory request or to a thread performing read memory requests.

公开(公告)号：US20180329650A1

公开(公告)日：2018-11-15

申请号：US15324107

申请日：2016-03-31

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Thomas Willhalm ,  Karthik Kumar ,  Martin P. Dimitrov ,  Raj K. Ramanujan

IPC: G06F3/06 ,  G06F12/0815

CPC classification number: G06F3/0659 ,  G06F3/0619 ,  G06F3/0625 ,  G06F3/0656 ,  G06F3/067 ,  G06F3/0688 ,  G06F12/0815 ,  G06F2212/621 ,  Y02D10/154

Abstract: Methods and apparatus related to fabric resiliency support for atomic writes of many store operations to remote nodes are described. In one embodiment, non-volatile memory stores data corresponding to a plurality of write operations. A first node includes logic to perform one or more operations (in response to the plurality of write operations) to cause storage of the data at a second node atomically. The plurality of write operations are atomically bound to a transaction and the data is written to the non-volatile memory in response to release of the transaction. Other embodiments are also disclosed and claimed.

公开(公告)号：US20180285260A1

公开(公告)日：2018-10-04

申请号：US15476866

申请日：2017-03-31

Applicant: Intel Corporation

Inventor： Patrick Lu ,  Karthik Kumar ,  Francesc Guim Bernat ,  Thomas Willhalm

IPC: G06F12/06 ,  G06F12/0873 ,  G06F12/0868 ,  G06F12/0891 ,  G06F12/02 ,  G06F13/16 ,  G06F13/42

CPC classification number: G06F12/0638 ,  G06F12/0246 ,  G06F12/0868 ,  G06F12/0873 ,  G06F12/0891 ,  G06F13/1694 ,  G06F13/4239 ,  G06F2212/7201

Abstract: Persistent caching of memory-side cache content for devices, systems, and methods are disclosed and discussed. In a system including both a volatile memory (VM) and a nonvolatile memory (NVM), both mapped to the system address space, software applications directly access the NVM, and a portion of the VM is used as a memory-side cache (MSC) for the NVM. When power is lost, at least a portion of the MSC cache contents is copied to a storage region in the NVM, which is restored to the MSC upon system reboot.

公开(公告)号：US20180284996A1

公开(公告)日：2018-10-04

申请号：US15474044

申请日：2017-03-30

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Mark Schmisseur ,  Karthik Kumar ,  Thomas Willhalm ,  Lidia Warnes

IPC: G06F3/06

CPC classification number: G06F3/067 ,  G06F3/0605 ,  G06F3/0631 ,  G06F9/50

Abstract: The present disclosure relates to a dynamically composable computing system. The dynamically composable computing system comprises at least one compute sled including a set of respective local computing hardware resources; a plurality of disaggregated memory modules; at least one disaggregated memory acceleration logic configured to perform one or more predefined computations on data stored in one or more of the plurality of disaggregated memory modules; and a resource manager module configured to assemble a composite computing node by associating, in accordance with requirements of a user, at least one of the plurality of disaggregated memory modules with the disaggregated memory acceleration logic to provide at least one accelerated disaggregated memory module and connecting the least one accelerated disaggregated memory module to the compute sled.

公开(公告)号：US20180284993A1

公开(公告)日：2018-10-04

申请号：US15476875

申请日：2017-03-31

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Kshitij A. Doshi ,  Daniel Rivas Barragan

IPC: G06F3/06 ,  G06F9/54 ,  H04L29/08 ,  G06F9/48 ,  G06F9/45

Abstract: Technology for a controller in a storage area network (SAN) node operable to perform data requests is described. The controller can receive a data request from a remote node. The data request can specify a data payload and a type of operation associated with the data request. The controller can select a kernel from a kernel table stored in the memory based on a set of rules. The kernel can be matched to the data request in accordance with the set of rules. The kernel can be configured using a bit stream. The controller can execute the kernel in order to perform the data request in accordance with the data payload and the type of operation.

公开(公告)号：US20180267878A1

公开(公告)日：2018-09-20

申请号：US15460385

申请日：2017-03-16

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Karthik Kumar ,  Thomas Willhalm ,  Daniel Rivas Barragan ,  Patrick Lu

IPC: G06F11/34 ,  G06F11/30 ,  H03K19/177

CPC classification number: G06F11/3409 ,  G06F11/3017 ,  H03K19/1776 ,  H03K19/17764

Abstract: In one embodiment, a field programmable gate array (FPGA) includes: programmable logic to perform at least one function for a processor coupled to the FPGA; a performance monitor circuit including a set of performance monitors to be programmably associated with a first kernel to execute on the FPGA; and a monitor circuit to receive kernel registration information of the first kernel from the processor and program a first set of performance monitors for association with the first kernel based on the kernel registration information. Other embodiments are described and claimed.

公开(公告)号：US10038767B2

公开(公告)日：2018-07-31

申请号：US15260613

申请日：2016-09-09

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Karthik Kumar ,  Thomas Willhalm ,  Raj K. Ramanujan ,  Daniel Rivas Barragan

IPC: H04L12/50 ,  H04L29/08 ,  H04L1/16

CPC classification number: H04L69/324 ,  G06F15/173 ,  H04L1/1642 ,  H04L12/50 ,  H04L45/28 ,  H04L45/745 ,  H04L49/00

Abstract: Technologies for using fabric supported sequencers in fabric architectures includes a network switch communicatively coupled to a plurality of computing nodes. The network switch is configured to receive an sequencer access message from one of the plurality of computing nodes that includes an identifier of a sequencing counter corresponding to a sequencer session and one or more operation parameters. The network switch is additionally configured to perform an operation on a value associated with the identifier of the sequencing counter as a function of the one or more operation parameters, increment the identifier of the sequencing counter, and associate a result of the operation with the incremented identifier of the sequencing counter. The network switch is further configured to transmit an acknowledgment of successful access to the computing node that includes the result of the operation and the incremented identifier of the sequencing counter. Other embodiments are described herein.

公开(公告)号：US20180150256A1

公开(公告)日：2018-05-31

申请号：US15716790

申请日：2017-09-27

Applicant: Intel Corporation

Inventor： Karthik Kumar ,  Francesc Guim Bernat ,  Thomas Willhalm ,  Mark A. Schmisseur

IPC: G06F3/06

CPC classification number: G06F3/0641 ,  G06F3/0604 ,  G06F3/0608 ,  G06F3/0611 ,  G06F3/0613 ,  G06F3/0617 ,  G06F3/0647 ,  G06F3/065 ,  G06F3/0653 ,  G06F3/067 ,  G06F7/06 ,  G06F8/65 ,  G06F8/654 ,  G06F8/656 ,  G06F8/658 ,  G06F9/3851 ,  G06F9/3891 ,  G06F9/4401 ,  G06F9/4881 ,  G06F9/5038 ,  G06F9/505 ,  G06F9/544 ,  G06F11/0709 ,  G06F11/0751 ,  G06F11/079 ,  G06F11/1453 ,  G06F11/3006 ,  G06F11/3034 ,  G06F11/3055 ,  G06F11/3409 ,  G06F12/023 ,  G06F12/0284 ,  G06F12/0692 ,  G06F13/1652 ,  G06F15/80 ,  G06F16/1744 ,  G06F21/57 ,  G06F21/6218 ,  G06F21/73 ,  G06F21/76 ,  G06F2212/401 ,  G06F2212/402 ,  G06F2221/2107 ,  G06T1/20 ,  G06T1/60 ,  G06T9/005 ,  H01R13/4538 ,  H01R13/631 ,  H03K19/1731 ,  H03M7/3084 ,  H03M7/40 ,  H03M7/42 ,  H03M7/60 ,  H03M7/6011 ,  H03M7/6017 ,  H03M7/6029 ,  H04L9/0822 ,  H04L12/2881 ,  H04L12/4633 ,  H04L41/044 ,  H04L41/046 ,  H04L41/0816 ,  H04L41/0853 ,  H04L41/0896 ,  H04L41/12 ,  H04L41/142 ,  H04L43/04 ,  H04L43/06 ,  H04L43/08 ,  H04L43/0894 ,  H04L47/20 ,  H04L47/2441 ,  H04L47/78 ,  H04L49/104 ,  H04L61/2007 ,  H04L63/1425 ,  H04L67/10 ,  H04L67/1014 ,  H04L67/327 ,  H04L67/36 ,  H05K7/1452 ,  H05K7/1487

Abstract: Technologies for providing data deduplication in a disaggregated architecture include a network device. The network device is to receive, from a compute sled, a request to write a data block to one or more data storage sleds and determine, for each of one or more data sub-blocks within the data block and from deduplication data indicative of physical addresses of data sub-blocks, whether each data sub-block is already stored in a data storage device of a data storage sled. Additionally, the network device is to write, in the deduplication data and in response to a determination that a data sub-block is already stored in a data storage device, a pointer to a physical address of the already-stored data sub-block in association with a logical address of the data sub-block.

公开(公告)号：US20180095906A1

公开(公告)日：2018-04-05

申请号：US15283284

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Kshitij A. Doshi ,  Francesc Guim Bernat ,  Daniel Rivas Barragan

IPC: G06F13/16 ,  G06F3/06 ,  G06F12/1027 ,  G06F13/18 ,  G06F12/14

CPC classification number: G06F13/1663 ,  G06F3/0619 ,  G06F3/0659 ,  G06F3/067 ,  G06F12/0815 ,  G06F12/1027 ,  G06F12/1433 ,  G06F13/18 ,  G06F2212/1052 ,  G06F2212/68

Abstract: Apparatuses, systems, and methods for coherently sharing data across a multi-node network is described. A coherency protocol for such data sharing can include identifying a memory access request from a requesting node for an I/O block of data in a shared I/O address space of a multi-node network, determining a logical ID and a logical offset of the I/O block, identifying an owner of the I/O block, negotiating permissions with the owner of the I/O block, and performing the memory access request on the I/O block.