公开(公告)号：US11769735B2

公开(公告)日：2023-09-26

申请号：US16274086

申请日：2019-02-12

Applicant: Intel Corporation

Inventor： Srinivas Pietambaram ,  Gang Duan ,  Deepak Kulkarni ,  Rahul Manepalli ,  Xiaoying Guo

IPC: H01L21/56 ,  H01L23/00 ,  H01L21/48 ,  H01L23/31 ,  H01L23/538

CPC classification number: H01L23/562 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3121 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/214 ,  H01L2924/3511

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, the electronic package comprises a mold layer having a first surface and a second surface opposite the first surface, and a plurality of first dies embedded in the mold layer. In an embodiment, each of the plurality of first dies has a surface that is substantially coplanar with the first surface of the mold layer. In an embodiment, the electronic package further comprises a second die embedded in the mold layer. In an embodiment, the second die is positioned between the plurality of first dies and the second surface of the mold layer.

公开(公告)号：US20230197679A1

公开(公告)日：2023-06-22

申请号：US17558457

申请日：2021-12-21

Applicant: Intel Corporation

Inventor： Jeremy Ecton ,  Jason M. Gamba ,  Brandon C. Marin ,  Srinivas V. Pietambaram ,  Xiaoxuan Sun ,  Omkar G. Karhade ,  Xavier Francois Brun ,  Yonggang Li ,  Suddhasattwa Nad ,  Bohan Shan ,  Haobo Chen ,  Gang Duan

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/538

CPC classification number: H01L25/0652 ,  H01L24/16 ,  H01L24/14 ,  H01L24/73 ,  H01L24/13 ,  H01L23/5383 ,  H01L2224/16227 ,  H01L2224/14177 ,  H01L2224/73204 ,  H01L2224/13111 ,  H01L2924/01079 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/01083 ,  H01L2924/01049 ,  H01L2924/01031

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first die, having a first surface and an opposing second surface, in a first layer; a redistribution layer (RDL) on the first layer, wherein the RDL includes conductive vias having a greater width towards a first surface of the RDL and a smaller width towards an opposing second surface of the RDL; wherein the first surface of the RDL is electrically coupled to the second surface of the first die by first solder interconnects having a first solder; and a second die in a second layer on the RDL, wherein the second die is electrically coupled to the RDL by second solder interconnects having a second solder, wherein the second solder is different than the first solder.

公开(公告)号：US20230197543A1

公开(公告)日：2023-06-22

申请号：US17557142

申请日：2021-12-21

Applicant: Intel Corporation

Inventor： Liang He ,  Yue Deng ,  Jung Kyu Han ,  Gang Duan

IPC: H01L23/29 ,  H01L23/18

CPC classification number: H01L23/291 ,  H01L23/18 ,  H01L23/298

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first die, having a first surface and an opposing second surface with conductive contacts, in a first layer; a first material surrounding the first die and extending along a thickness of the first die from the second surface, and wherein the first material includes first particles having an average diameter between 200 and 500 nanometers; a second material surrounding the first die and extending along the thickness of the first die from the first surface, and wherein the second material includes second particles having an average diameter between 0.5 and 12 microns; an interface portion, between the first and second materials, including the first and second particles; and a second die, in a second layer on the first layer, electrically coupled to the conductive contacts on the first die.

公开(公告)号：US20230090449A1

公开(公告)日：2023-03-23

申请号：US17448693

申请日：2021-09-23

Applicant: Intel Corporation

Inventor： Suddhasattwa Nad ,  Gang Duan ,  Jeremy Ecton ,  Brandon Marin ,  Ravindranath Mahajan

IPC: H01L23/00

Abstract: Methods, systems, apparatus, and articles of manufacture to produce nano-roughened integrated circuit packages are disclosed. An example integrated circuit (IC) package includes a substrate, a semiconductor die, and a metal interconnect to electrically couple the semiconductor die to the substrate, the metal interconnect including a nano-roughened surface.

公开(公告)号：US20230089684A1

公开(公告)日：2023-03-23

申请号：US17479369

申请日：2021-09-20

Applicant: Intel Corporation

Inventor： Yosuke Kanaoka ,  Robin Mcree ,  Gang Duan ,  Gautam Medhi ,  Huang-Ta Chen

IPC: H01L23/544

Abstract: A substrate for an electronic device may include one or more layers. The substrate may include a cavity defined in the substrate. The cavity may be adapted to receive a semiconductor die. The substrate may include a fiducial mark positioned proximate the cavity. The fiducial mark may be exposed on a first surface of the substrate. The fiducial mark may include a first region including a dielectric filler material. The fiducial mark may include a second region including a conductive filler material. In an example, the second region surrounds the first region. In another example, the dielectric filler material has a lower reflectivity in comparison to the conductive filler material to provide a contrast between the first region and the second region.

公开(公告)号：US20230086180A1

公开(公告)日：2023-03-23

申请号：US17479854

申请日：2021-09-20

Applicant: Intel Corporation

Inventor： Onur Ozkan ,  Edvin Cetegen ,  Steve Cho ,  Nicholas S. Haehn ,  Jacob Vehonsky ,  Gang Duan

IPC: H01L23/00

Abstract: A semiconductor device may include a first plate-like element having a first substantially planar connection surface with a first connection pad and a second plate-like element having a second substantially planar connection surface with a second connection pad corresponding to the first connection pad. The device may also include a connection electrically and physically coupling the first and second plate-like elements and arranged between the first and second connection pads. The connection may include a deformed elongate element arranged on the first connection pad and extending toward the second connection pad and solder in contact with the second connection pad and the elongate element.

公开(公告)号：US11527484B2

公开(公告)日：2022-12-13

申请号：US17078897

申请日：2020-10-23

Applicant: Intel Corporation

Inventor： Jesse C. Jones ,  Gang Duan ,  Jason Gamba ,  Yosuke Kanaoka ,  Rahul N. Manepalli ,  Vishal Shajan

IPC: H01L23/544 ,  H01L21/762 ,  H01L23/538

Abstract: An electronic device includes a substrate, and the substrate may include one or more layers. The one or more layers may include a dielectric material and may include one or more electrical traces. The electronic device may include a layer of conductive material, and the layer of conductive material may define a void in the conductive material. The electronic device may include a fiducial mark, and the fiducial mark may include a filler material positioned in the void defined by the conductive material. The fiducial mark may be coupled to the layer of conductive material. The filler material may have a lower reflectivity in comparison to the conductive material, for instance to provide a contrast with the conductive material.

公开(公告)号：US20220254559A1

公开(公告)日：2022-08-11

申请号：US17731498

申请日：2022-04-28

Applicant: Intel Corporation

Inventor： Srinivas Venkata Ramanuja Pietambaram ,  Kristof Darmawikarta ,  Gang Duan ,  Yonggang Li ,  Sameer Paital

IPC: H01F27/26 ,  H01F27/42 ,  H01L21/768 ,  H01L23/64

Abstract: Described are microelectronic devices including an embedded microelectronic package for use as an integrated voltage regulator with a microelectronic system. The microelectronic package can include a substrate and a magnetic foil. The substrate can define at least one layer having one or more of electrically conductive elements separated by a dielectric material. The magnetic foil can have ferromagnetic alloy ribbons and can be embedded within the substrate adjacent to the one or more of electrically conductive elements. The magnetic foil can be positioned to interface with and be spaced from the one or more of electrically conductive element.

公开(公告)号：US11227849B2

公开(公告)日：2022-01-18

申请号：US16582865

申请日：2019-09-25

Applicant: Intel Corporation

Inventor： Brandon C Marin ,  Srinivas V. Pietambaram ,  Kristof Darmawikarta ,  Gang Duan ,  Sameer Paital

IPC: H01L23/00

Abstract: Disclosed embodiments include a catalyst-doped mold interconnect system, where activated catalyst particles that line via and trace corridors, are used for electroless-plating formation of both liners and vias and traces that also electrolessly plate onto the liners. Photolithographically formed interconnects can be mingled with laser-ablation form-factor vias and traces within a single stratum of a catalyst doped mold interconnect system.

公开(公告)号：US20210028080A1

公开(公告)日：2021-01-28

申请号：US16522494

申请日：2019-07-25

Applicant: Intel Corporation

Inventor： Srinivas PIETAMBARAM ,  Robert L. Sankman ,  Rahul Manepalli ,  Gang Duan ,  Debendra Mallik

IPC: H01L23/15 ,  H01L23/538 ,  H01L23/498 ,  H01L23/31 ,  H01L23/495

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, the electronic package comprises a glass substrate, with a plurality of first pads on a first surface of the glass substrate, a plurality of second pads on a second surface of the glass substrate that is opposite from the first surface, a plurality of through glass vias (TGVs), wherein each TGV electrically couples a first pad to a second pad, wherein the plurality of first pads have a first pitch, and wherein the plurality of second pads have a second pitch that is greater than the first pitch, a bridge substrate over the glass substrate, a first die electrically coupled to first pads and the bridge substrate, and a second die electrically coupled to first pads and the bridge substrate, wherein the bridge substrate electrically couples the first die to the second die.