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    STIFFENER BUILD-UP LAYER PACKAGE
    91.
    发明申请
    STIFFENER BUILD-UP LAYER PACKAGE 审中-公开

    公开(公告)号：US20200006253A1

    公开(公告)日：2020-01-02

    申请号：US16419683

    申请日：2019-05-22

    Applicant: Intel Corporation

    Inventor： Bok Eng Cheah ,  Jackson Chung Peng Kong ,  Jenny Shio Yin Ong ,  Seok Ling Lim

    IPC: H01L23/00 ,  H01L23/522

    Abstract: To maintain the integrity of electrical contacts at a build-up layer of a chip package, while reducing electrical interference caused by a chip connected to the build-up layer, the chip package can include a stiffener formed from an electrically conductive material and positioned between the chip and the build-up layer. The chip can electrically connect to the build-up layer through electrical connections that extend through the stiffener. Compared with a stiffener that extends only over a single chip of the chip package, the present stiffener can help prevent warpage or other mechanical deformities that can degrade electrical contacts away from the chip at the build-up layer. Compared with a stiffener that extends only over an area away from the chip, such as a peripheral area, the present stiffener can help reduce electrical interference in an area of the build-up layer near the chip.

    SUBSTRATE WITH GRADIATED DIELECTRIC FOR REDUCING IMPEDANCE MISMATCH
    92.
    发明申请
    SUBSTRATE WITH GRADIATED DIELECTRIC FOR REDUCING IMPEDANCE MISMATCH 审中-公开

    公开(公告)号：US20190355681A1

    公开(公告)日：2019-11-21

    申请号：US16473962

    申请日：2017-12-19

    Applicant: Intel Corporation

    Inventor： Jackson Chung Peng Kong ,  Bok Eng Cheah ,  Ping Ping Ooi ,  Kooi Chi Ooi

    IPC: H01L23/66 ,  H01L23/498 ,  H01L21/48

    Abstract: An electronic circuit including a substrate having a first dielectric characteristic. The substrate can include a first side and a second side. An intermediary material can be disposed within the substrate. For instance, the intermediary material can be located between the first side and the second side. The intermediary material can include a second dielectric characteristic, where the second dielectric characteristic is different than the first dielectric characteristic. A first conductive layer can be disposed on the first side, and a second conductive layer can be disposed on the second side. A conductive path can be electrically coupled between the first conductive layer and the second conductive layer. The conductive path can be in contact with at least a portion of the intermediary material.

    Routing-over-void-T-line-compensation
    93.
    发明授权
    Routing-over-void-T-line-compensation 有权

    公开(公告)号：US10484231B2

    公开(公告)日：2019-11-19

    申请号：US16021292

    申请日：2018-06-28

    Applicant: Intel Corporation

    Inventor： Khang Choong Yong ,  Bok Eng Cheah ,  Jackson Chung Peng Kong ,  Stephen Harvey Hall ,  Yun Rou Lim

    IPC: H04L29/10 ,  H05K1/02 ,  H01R13/66

    Abstract: Apparatus and methods are provided for ameliorating distortion issues associated with a conductor that passes over a void in a reference plane. In an example, the signal conductor can include a first part routed over the major surface of a first side of the reference plane structure on a first side of the void and that approaches a first edge of the reference plane structure with a first trajectory, a second part routed over the major surface of the reference plane structure on a second side of the void and that approaches a second edge of the reference plane structure with a second trajectory, and a third portion connecting the first portion with the second portion, the third portion spanning the void, and having a plurality of spurs extending from a body of the third portion.

    MICRO-HINGE FOR AN ELECTRONIC DEVICE
    95.
    发明申请
    MICRO-HINGE FOR AN ELECTRONIC DEVICE 审中-公开

    公开(公告)号：US20190093402A1

    公开(公告)日：2019-03-28

    申请号：US16012469

    申请日：2018-06-19

    Applicant: Intel Corporation

    Inventor： Bok Eng Cheah ,  Howe Yin Loo ,  Min Suet Lim ,  Jackson Chung Peng Kong ,  Poh Tat Oh

    IPC: E05D3/06 ,  H05K5/02 ,  E05D11/00 ,  G06F1/16 ,  G06F1/32

    Abstract: Particular embodiments described herein provide for an electronic device, such as a notebook computer or laptop, which includes a circuit board coupled to a plurality of electronic components (which includes any type of components, elements, circuitry, etc.). One particular example implementation of the electronic device may include a low profile hinge design that includes a micro-hinge. The micro-hinge can couple a first element to a second element and can include a first attachment that couples to the first element, a second attachment that couples to the second element, and a plurality of linkages that couples the first attachment to the second attachment. The low profile hinge can further include a plurality of micro-hinges and a plurality of support rods.

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