公开(公告)号：US11853205B2

公开(公告)日：2023-12-26

申请号：US18172205

申请日：2023-02-21

Applicant: Micron Technology, Inc.

Inventor： Kishore Kumar Muchherla ,  Peter Feeley ,  Ashutosh Malshe ,  Daniel J. Hubbard ,  Christopher S. Hale ,  Kevin R. Brandt ,  Sampath K. Ratnam ,  Yun Li ,  Marc S. Hamilton

IPC: G06F3/00 ,  G06F12/02 ,  G06F12/0891 ,  G06F3/06 ,  G06F12/06 ,  G06F12/00 ,  G11C11/56

CPC classification number: G06F12/0253 ,  G06F3/064 ,  G06F3/0629 ,  G06F3/0634 ,  G06F3/0688 ,  G06F3/0689 ,  G06F12/00 ,  G06F12/0646 ,  G06F12/0891 ,  G06F2212/1044 ,  G06F2212/2022 ,  G06F2212/7205 ,  G11C11/5621 ,  G11C2211/5641

Abstract: A memory system includes a memory array having a plurality of memory cells; and a controller coupled to the memory array, the controller configured to: designate a storage mode for a target set of memory cells based on valid data in a source block, wherein the target set of memory cells are configured with a capacity to store up to a maximum number of bits per cell, and the storage mode is for dynamically configuring the target set of memory cells in as cache memory that stores a number of bits less per cell than the corresponding maximum capacity.

公开(公告)号：US11797441B2

公开(公告)日：2023-10-24

申请号：US17103419

申请日：2020-11-24

Applicant: Micron Technology, Inc.

Inventor： Ashutosh Malshe ,  Sampath K. Ratnam ,  Kishore Kumar Muchherla ,  Peter Feeley

IPC: G06F12/08 ,  G06F12/0802 ,  G06F12/02

CPC classification number: G06F12/0802 ,  G06F12/0253 ,  G06F2212/7205

Abstract: An exempt portion of a data cache of a memory sub-system is identified. The exempt portion includes a first set of data blocks comprising first data written by a host system to the data cache. A collected portion of the data cache of the memory sub-system is identified. The collected portion includes a second set of data blocks comprising second data written by the host system. A media management operation is performed on the collected portion of the data cache to relocate the second data to a storage area of the memory sub-system that is at a higher data density than the data cache, wherein the exempt portion of the data cache is exempt from the media management operation.

公开(公告)号：US20230325273A1

公开(公告)日：2023-10-12

申请号：US18207525

申请日：2023-06-08

Applicant: Micron Technology, Inc.

Inventor： Kishore Kumar Muchherla ,  Shane Nowell ,  Mustafa N. Kaynak ,  Sampath K. Ratnam ,  Peter Feeley ,  Sivagnanam Parthasarathy ,  Devin M. Batutis ,  Xiangang Luo

IPC: G06F11/07

CPC classification number: G06F11/0793 ,  G06F11/0751 ,  G06F11/0727

Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations including detecting a read error with respect to data residing in a first block of the memory device, wherein the first block is associated with a voltage offset bin; determining a most recently performed error-handling operation performed on a second block associated with the voltage offset bin; and performing the error-handling to recover the data.

公开(公告)号：US11782847B2

公开(公告)日：2023-10-10

申请号：US17898138

申请日：2022-08-29

Applicant: Micron Technology, Inc.

Inventor： Kishore Kumar Muchherla ,  Peter Feeley ,  Sampath K. Ratnam ,  Ashutosh Malshe

IPC: G06F12/123 ,  G06F12/02 ,  G06F11/30

CPC classification number: G06F12/123 ,  G06F11/3037 ,  G06F12/0246 ,  G06F12/0253 ,  G06F2212/70 ,  G06F2212/7205 ,  G06F2212/7209

Abstract: A first block that is assigned a first sequence identifier can be identified. A determination can be made as to whether the assigned first sequence identifier satisfies a threshold sequence identifier condition that corresponds to a difference between the first sequence identifier assigned to the first block and second sequence identifier assigned to a second block. In response to determining that the assigned first sequence identifier satisfies the threshold sequence identifier condition, a media management operation can be performed on the first block.

公开(公告)号：US11748013B2

公开(公告)日：2023-09-05

申请号：US17949977

申请日：2022-09-21

Applicant: Micron Technology, Inc.

Inventor： Kishore Kumar Muchherla ,  Mustafa N. Kaynak ,  Jiangang Wu ,  Sampath K. Ratnam ,  Sivagnanam Parthasarathy ,  Peter Feeley ,  Karl D. Schuh

IPC: G06F3/06 ,  G11C16/10 ,  G11C16/04

CPC classification number: G06F3/064 ,  G06F3/0625 ,  G06F3/0659 ,  G06F3/0673 ,  G11C16/10 ,  G11C16/0483

Abstract: An initial value of a power cycle count associated with the memory device is identified. The power cycle count is incremented responsive to detecting a powering up of the memory device. Responsive to programming a block residing in the memory device, the block is associated with a current block family associated with the memory device. A currently value of the power cycle count is determined. Responsive to determining that a difference between the initial value of the power cycle count and the current value of the power cycle count satisfies a predefined condition, the current block family is closed.

公开(公告)号：US11726874B2

公开(公告)日：2023-08-15

申请号：US17249399

申请日：2021-03-01

Applicant: Micron Technology, Inc.

Inventor： Vamsi Rayaprolu ,  Sivagnanam Parthasarathy ,  Sampath K. Ratnam ,  Peter Feeley ,  Kishore Kumar Muchherla

IPC: G06F11/10 ,  G06F11/00 ,  G06F3/06

CPC classification number: G06F11/1076 ,  G06F3/064 ,  G06F3/0619 ,  G06F3/0673 ,  G06F11/1004 ,  G06F11/1012

Abstract: A request to retrieve user data stored at a memory device is received and a first error control operation associated with the user data is performed. An indication of a failure of the first error control operation is received, and in response, a subset of system data stored at the memory device is identified. A second error control operation is performed on the subset of the system data to retrieve the subset of the system data stored at the memory device, and the user data is read by using the subset of the system data retrieved based on the performing of the second error control operation.

公开(公告)号：US11676664B2

公开(公告)日：2023-06-13

申请号：US17883538

申请日：2022-08-08

Applicant: Micron Technology, Inc.

Inventor： Kishore Kumar Muchherla ,  Sampath K. Ratnam ,  Shane Nowell ,  Sivagnanam Parthasarathy ,  Mustafa N. Kaynak ,  Karl D. Schuh ,  Peter Feeley ,  Jiangang Wu

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/20 ,  G11C16/32 ,  G11C16/30 ,  G11C16/26

CPC classification number: G11C16/102 ,  G11C16/20 ,  G11C16/26 ,  G11C16/30 ,  G11C16/32 ,  G11C16/3495

Abstract: A processing device of a memory sub-system is configured to detect a power on event that is associated with a memory device and indicates that power has been restored to the memory device; estimate a duration of a power off state preceding the power on event associated with the memory device; and update voltage bin assignments of a plurality of blocks associated with the memory device based on the duration of the power off state.

公开(公告)号：US11675511B2

公开(公告)日：2023-06-13

申请号：US17846378

申请日：2022-06-22

Applicant: Micron Technology, Inc.

Inventor： Michael Sheperek ,  Bruce A. Liikanen ,  Peter Feeley ,  Larry J. Koudele ,  Shane Nowell ,  Steven Michael Kientz

IPC: G06F3/06

CPC classification number: G06F3/064 ,  G06F3/0604 ,  G06F3/0679

Abstract: An example memory sub-system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is configured to perform operations comprising assigning a plurality of data streams to a block family comprising a plurality of blocks of a memory device; responsive to programming a first block associated with a first data stream of the plurality of data streams, associating the first block with the block family; and responsive to programming a second block associated with a second data stream of the plurality of data streams, associating the second block with the block family.

公开(公告)号：US20230122275A1

公开(公告)日：2023-04-20

申请号：US18083992

申请日：2022-12-19

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kishore Kumar Muchherla ,  Mustafa N. Kaynak ,  Sivagnanam Parthasarathy ,  Xiangang Luo ,  Peter Feeley ,  Devin M. Batutis ,  Jiangang Wu ,  Sampath K. Ratnam ,  Shane Nowell ,  Karl D. Schuh

IPC: G11C29/50 ,  G06F12/02 ,  G11C16/26 ,  G11C29/02 ,  G11C7/10

Abstract: A method includes initiating a voltage calibration scan with respect to a block of a memory device, wherein the block is assigned to a first bin associated with a first set of read voltage offsets, and wherein the first bin is designated as a current bin, measuring a value of a data state metric for the block based on a second set of read voltage offsets associated with a second bin having an index value higher than the first bin, determining whether the value is less than a current value of the data state metric measured based on the first set of read voltage offsets, and in response to determining that the value is less than the current value, designating the second bin as the current bin.

公开(公告)号：US11586357B2

公开(公告)日：2023-02-21

申请号：US17332468

申请日：2021-05-27

Applicant: Micron Technology, Inc.

Inventor： Kishore K. Muchherla ,  Ashutosh Malshe ,  Preston A. Thomson ,  Michael G. Miller ,  Sampath K. Ratnam ,  Renato C. Padilla ,  Peter Feeley

IPC: G06F3/06 ,  G11C16/10 ,  G11C16/16 ,  G11C16/34 ,  G11C11/56

Abstract: The present disclosure includes memory blocks erasable in a single level cell mode. A number of embodiments include a memory comprising a plurality of mixed mode blocks and a controller. The controller may be configured to identify a particular mixed mode block for an erase operation and, responsive to a determined intent to subsequently write the particular mixed mode block in a single level cell (SLC) mode, perform the erase operation in the SLC mode.