公开(公告)号：US20230069559A1

公开(公告)日：2023-03-02

申请号：US17462605

申请日：2021-08-31

Applicant: Micron Technology, Inc.

Inventor： Zhongguang Xu ,  Jian Huang ,  Tingjun Xie ,  Murong Lang ,  Zhenming Zhou

IPC: G06F3/06

Abstract: A request to perform a memory access operation on a plurality of memory cells of a memory device is receive. A request type associated with the memory access operation is determined. In response to determining that the request type associated with the request type associated with the memory access operation is a first request type, an error recovery operation associated with the first request type is performed. In response to determining that the request type associated with the memory access operation is a second request type, an error recovery operation associated with the second request type is performed.

公开(公告)号：US20220398022A1

公开(公告)日：2022-12-15

申请号：US17348226

申请日：2021-06-15

Applicant: Micron Technology, Inc.

Inventor： Zhenming Zhou ,  Seungjune Jeon ,  Zhenlei Shen

IPC: G06F3/06 ,  G06F12/10 ,  G06F7/58

Abstract: Systems and methods are disclosed including a processing device operatively coupled to memory device. The processing device performs operations comprising receiving a memory access command specifying a logical address; determining a physical address associated with the logical address; determining a portion of the memory device that is referenced by the physical address; determine an endurance factor associated with the portion; and increasing, by a value derived from the endurance factor, a media management metric associated with a management unit of the memory device, wherein the management unit is referenced by the physical address.

公开(公告)号：US11520657B1

公开(公告)日：2022-12-06

申请号：US17445392

申请日：2021-08-18

Applicant: Micron Technology, Inc.

Inventor： Zhenlei Shen ,  Tingjun Xie ,  Frederick Adi ,  Wei Wang ,  Zhenming Zhou

IPC: G06F11/00 ,  G06F11/10 ,  G06F11/07

Abstract: A first error rate based on a first read operation performed on a memory device is obtained. An individual data unit of the memory device that satisfies a first threshold criterion associated with a defect candidate is determined. A defect verification operation on the individual data unit to obtain a second error rate is performed. The individual data unit that satisfies a second threshold criterion associated with a defect is determined.

公开(公告)号：US20220365684A1

公开(公告)日：2022-11-17

申请号：US17302851

申请日：2021-05-13

Applicant: Micron Technology, Inc.

Inventor： Zhongguang Xu ,  Zhenlei Shen ,  Tingjun Xie ,  Seungjune Jeon ,  Murong Lang ,  Zhenming Zhou

IPC: G06F3/06 ,  G06F11/30 ,  G06F11/07

Abstract: Respective life expectancies of a first data unit and a second data unit of the memory device is obtained. A first initial age value corresponding to the first data unit and a second initial age value corresponding to the second data unit are determined. A lower one of the first initial age value and the second initial age value is identified. A first media management operation on a corresponding one of the first data unit or the second data unit associated with the lower one of the first initial age value and the second initial age value is performed. A second media management operation on the first data unit and the second data unit is performed.

公开(公告)号：US20220137854A1

公开(公告)日：2022-05-05

申请号：US17088280

申请日：2020-11-03

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Murong Lang ,  Jian Huang ,  Zhongguang Xu ,  Zhenming Zhou

IPC: G06F3/06

Abstract: An operation timing condition associated with a memory device to be installed at a memory sub-system is determined. The memory device can include a cross-point array of non-volatile memory cells. The operation timing condition corresponds to a first operation delay timing margin setting for the cross-point array of non-volatile memory cells. A first set of memory access operations is performed at the cross-point array of non-volatile memory cells according to a second operation delay timing margin setting that is lower than the first operation delay timing margin setting. A first number of errors that occurred during performance of the first set of memory access operations is determined. In response to a determination that the first number of errors satisfies an error condition, a first quality rating is assigned for the memory device. In response to a determination that the first number of errors does not satisfy the error criterion, further testing is performed for the cross-point array of non-volatile memory cells based on one or more power level settings.

公开(公告)号：US20220066924A1

公开(公告)日：2022-03-03

申请号：US17005164

申请日：2020-08-27

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Mikai Chen ,  Zhenlei Shen ,  Murong Lang ,  Zhenming Zhou

IPC: G06F12/02 ,  G06F11/07 ,  G06F11/30

Abstract: A processing device of a memory sub-system performs an operation including obtaining, at a first time, a first scaling factor for a data unit of a set of data units of a memory device. The first scaling factor is associated with a first number of write operations performed at the data unit and a first number of read operations performed at the data unit. The processing device also performs an operation including calculating a first media management metric based on at least the first scaling factor, the first number of write operations, and the first number of read operations. In response to determining that the first media management metric satisfies a media management criterion, the processing device performs a media management operation on the data unit.

公开(公告)号：US11183267B2

公开(公告)日：2021-11-23

申请号：US16510778

申请日：2019-07-12

Applicant: Micron Technology, Inc.

Inventor： Jian Huang ,  Zhenming Zhou

IPC: G11C29/00 ,  G11C29/44 ,  G11C29/38

Abstract: A system includes a memory component, and a processing device coupled with the memory component. The processing device to identify a group of management units of the memory component, wherein the group of management units is included in a set of retired groups of management units, select a management unit from the group of management units, perform a media integrity check on the management unit to determine a failed bit count of the management unit, and in response to the failed bit count of the management unit failing to satisfy a threshold criterion, remove the group of management units from the set of retired groups of management units.

公开(公告)号：US11127481B1

公开(公告)日：2021-09-21

申请号：US16926167

申请日：2020-07-10

Applicant: Micron Technology, Inc.

Inventor： Murong Lang ,  Zhongguang Xu ,  Zhenming Zhou

IPC: G11C29/50 ,  G06F11/10 ,  G11C29/12 ,  G06F11/07 ,  G11C29/44

Abstract: A value corresponding to an operating characteristic of a memory sub-system is determined. The value is compared to a first threshold level to determine whether a first condition is satisfied. The value is also compared to a second threshold level to determine whether a second condition is satisfied. In response to satisfying the first condition, a read scrub operation associated with the memory sub-system is executed. In response to satisfying the second condition, a write scrub operation associated with the memory sub-system is executed.

公开(公告)号：US20210065824A1

公开(公告)日：2021-03-04

申请号：US17035501

申请日：2020-09-28

Applicant: Micron Technology, Inc.

Inventor： Zhenming Zhou ,  Murong Lang

IPC: G11C16/34 ,  G11C16/26 ,  G11C16/14 ,  G11C16/30 ,  G11C16/10 ,  G11C13/00 ,  G11C29/50

Abstract: A current demarcation voltage is determined, where the current demarcation voltage is to be applied to a memory cell for reading a state of the memory cell. Based on the current demarcation voltage and a space between a first threshold voltage distribution corresponding to a first state of the memory cell and a second threshold voltage distribution corresponding to a second state of the memory cell, a test demarcation voltage having a low error rate of reading the state of the memory cell is selected. The current demarcation voltage is set to correspond to the selected test demarcation voltage.

公开(公告)号：US20210064279A1

公开(公告)日：2021-03-04

申请号：US16552692

申请日：2019-08-27

Applicant: Micron Technology, Inc.

Inventor： Tingjun Xie ,  Zhenming Zhou ,  Zhenlei Shen ,  Chih-Kuo Kao

IPC: G06F3/06 ,  G11C7/10

Abstract: A processing device in a memory sub-system initiates read operations on each of a plurality of segments in a first region of the memory device during a first time interval, wherein at least a subset of the plurality of segments in the first region of the memory device are storing host data. The processing device further receives, as a result of at least one read operation, at least one data signal from a corresponding one of the plurality of segments in the first region of the memory device, and performs a signal calibration operation using the at least one data signal to synchronize one or more relevant signals with a reference clock signal used by the processing device.