公开(公告)号：US08114306B2

公开(公告)日：2012-02-14

申请号：US12470760

申请日：2009-05-22

Applicant: Joy Cheng ,  Kafai Lai ,  Wai-Kin Li ,  Young-Hye Na ,  Charles Rettner ,  Daniel P. Sanders ,  Da Yang

Inventor： Joy Cheng ,  Kafai Lai ,  Wai-Kin Li ,  Young-Hye Na ,  Charles Rettner ,  Daniel P. Sanders ,  Da Yang

IPC: H01L21/31 ,  H01L21/469 ,  B32B3/00 ,  B05D3/00

CPC classification number: H01L21/76816 ,  B81B2203/0353 ,  B81B2207/07 ,  B81C1/00031 ,  B81C2201/0149 ,  B81C2201/0198 ,  G03F7/40 ,  H01L21/0337 ,  H01L21/31144 ,  Y10S438/947

Abstract: Methods involving the self-assembly of block copolymers are described herein, in which by beginning with openings (in one or more substrates) that have a targeted CD (critical dimension), holes are formed, in either regular arrays or arbitrary arrangements. Significantly, the percentage variation in the average diameter of the formed holes is less than the percentage variation of the average diameter of the initial openings. The formed holes (or vias) can be transferred into the underlying substrate(s), and these holes may then be backfilled with material, such as a metallic conductor. Preferred aspects of the invention enable the creation of vias with tighter pitch and better CD uniformity, even at sub-22 nm technology nodes.

Abstract translation: 本文描述了涉及嵌段共聚物的自组装的方法，其中从具有目标CD（临界尺寸）的开口（在一个或多个衬底中）开始，以规则阵列或任意布置形成孔。 显着地，形成的孔的平均直径的百分比变化小于初始开口的平均直径的变化百分比。 形成的孔（或通孔）可以被转移到下面的基底中，然后这些孔可以用诸如金属导体的材料回填。 本发明的优选方面能够创建具有更紧的间距和更好的CD均匀性的通孔，即使在22nm以下的技术节点。

公开(公告)号：US08083953B2

公开(公告)日：2011-12-27

申请号：US11714336

申请日：2007-03-06

Applicant: Dan B. Millward ,  Eugene P. Marsh

Inventor： Dan B. Millward ,  Eugene P. Marsh

IPC: B44C1/22 ,  H01L21/302 ,  B82B3/00

CPC classification number: B81B1/00 ,  B81C1/00015 ,  B81C1/00031 ,  B81C2201/0149 ,  B81C2201/0198 ,  B82Y10/00 ,  B82Y30/00 ,  B82Y40/00 ,  C08L53/00 ,  G03F7/0002 ,  Y10S438/947 ,  Y10S977/888 ,  Y10S977/895 ,  Y10S977/90 ,  C08L2666/02

Abstract: Methods for fabricating sublithographic, nanoscale linear microchannel arrays over surfaces without defined features utilizing self-assembling block copolymers, and films and devices formed from these methods are provided. Embodiments of the methods use a multilayer induced ordering approach to align lamellar films to an underlying base film within trenches, and localized heating to anneal the lamellar-phase block copolymer film overlying the trenches and outwardly over the remaining surface.

Abstract translation: 提供了使用自组装嵌段共聚物在表面上制备亚光刻纳米线性微通道阵列而不具有限定特征的方法，以及由这些方法形成的膜和器件。 该方法的实施方案使用多层诱导排序方法将层状膜与沟槽内的底层膜对准，并且进行局部加热以使覆盖在沟槽上的层状相嵌段共聚物膜退出，并在剩余表面上向外退火。

公开(公告)号：US08080615B2

公开(公告)日：2011-12-20

申请号：US11765232

申请日：2007-06-19

Applicant: Dan B. Millward

Inventor： Dan B. Millward

IPC: C08L71/02

CPC classification number: G03F7/40 ,  B32B3/10 ,  B81C1/00031 ,  B81C2201/0149 ,  B81C2201/0198 ,  B82Y30/00 ,  C08G81/02 ,  G03F7/12

Abstract: Methods for fabricating a random graft PS-r-PEO copolymer and its use as a neutral wetting layer in the fabrication of sublithographic, nanoscale arrays of elements including openings and linear microchannels utilizing self-assembling block copolymers, and films and devices formed from these methods are provided. In some embodiments, the films can be used as a template or mask to etch openings in an underlying material layer.

Abstract translation: 用于制造无规接枝PS-r-PEO共聚物的方法及其在制备亚光刻纳米级元素阵列的元件中作为中性润湿层的用途，包括使用自组装嵌段共聚物的开口和线性微通道，以及由这些方法形成的膜和器件 被提供。 在一些实施例中，膜可以用作模板或掩模来蚀刻下层材料层中的开口。

公开(公告)号：US07977177B2

公开(公告)日：2011-07-12

申请号：US12330898

申请日：2008-12-09

Applicant: Yonghan Roh ,  Kyoungseob Kim ,  Seokwon Jeong ,  Hyungjin Kim ,  Sungha Park

Inventor： Yonghan Roh ,  Kyoungseob Kim ,  Seokwon Jeong ,  Hyungjin Kim ,  Sungha Park

IPC: H01L21/336

CPC classification number: H01L21/32139 ,  B81C1/00396 ,  B81C2201/0149 ,  B81C2201/0198 ,  B82Y10/00 ,  H01L21/0332 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/78

Abstract: Provided are methods of forming nano-devices. One of the methods includes forming a nano-scale self-assembly material layer on a substrate formed of at least one layer, forming a mask layer on the self-assembly material layer, performing a surface treatment process on the substrate using the mask layer as a mask, and removing the self-assembly material layer. Accordingly, it is possible to fabricate nano-devices through a nano-scale substrate patterning process, ion implantation process and etching process, without using a light source.

Abstract translation: 提供了形成纳米器件的方法。 其中一种方法包括在由至少一层形成的衬底上形成纳米级自组装材料层，在自组装材料层上形成掩模层，使用掩模层在衬底上进行表面处理工艺 掩模，并且去除自组装材料层。 因此，可以通过纳米级基板图案化工艺，离子注入工艺和蚀刻工艺制造纳米器件，而不使用光源。

公开(公告)号：US20110086297A1

公开(公告)日：2011-04-14

申请号：US12905857

申请日：2010-10-15

Applicant: Benjamin B. Yellen ,  Gennady Friedman

Inventor： Benjamin B. Yellen ,  Gennady Friedman

IPC: G03F1/00

CPC classification number: G03F1/54 ,  B81C1/00031 ,  B81C2201/0198 ,  B82Y10/00 ,  G03F1/50

Abstract: Magnetic nanoparticle masks for lithographic applications of a substrate and methods for producing such masks via defining regions of localized magnetic field maxima and minima on a substrate are provided. Also provided are methods for producing multi-component patterns on a substrate with the magnetic nanoparticle masks.

Abstract translation: 提供了用于基板的光刻应用的磁性纳米颗粒掩模和通过限定基板上的局部磁场最大值和最小值的区域来产生这种掩模的方法。 还提供了在具有磁性纳米颗粒掩模的基底上产生多组分图案的方法。

公开(公告)号：US07828986B2

公开(公告)日：2010-11-09

申请号：US11926722

申请日：2007-10-29

Applicant: Joy Cheng ,  Mark W. Hart ,  Hiroshi Ito ,  Ho-Cheol Kim ,  Robert Miller

Inventor： Joy Cheng ,  Mark W. Hart ,  Hiroshi Ito ,  Ho-Cheol Kim ,  Robert Miller

IPC: B44C1/22 ,  H01L21/302

CPC classification number: H01L21/0337 ,  B81C1/00031 ,  B81C2201/0149 ,  B81C2201/0198 ,  H01L21/0271 ,  H01L21/0332

Abstract: A method. A combination is provided of a block copolymer and additional material. The copolymer includes a first block of a first polymer covalently bonded to a second block of a second polymer. The additional material is miscible with the first polymer. The first polymer includes polystyrene and the second polymer includes poly(ethylene oxide). A first layer including polydimethylglutarimide is adhered onto a surface of a substrate including a dielectric coated silicon wafer. A film is formed of the combination directly onto a surface of the first layer. Nanostructures of the additional material self-assemble within the first polymer block. The film and the first layer are simultaneously etched. The nanostructures have an etch rate lower than an etch rate of the block copolymer and lower than an etch rate of the first layer. Portions of the film are removed. Features remain on the surface of the first layer.

Abstract translation: 一个方法。 提供了一种嵌段共聚物和另外的材料的组合。 共聚物包括共价键合到第二聚合物的第二嵌段的第一聚合物的第一嵌段。 附加材料与第一聚合物混溶。 第一聚合物包括聚苯乙烯，第二聚合物包括聚（环氧乙烷）。 包括聚二甲基戊二酰亚胺的第一层粘附到包括电介质涂覆的硅晶片的基材的表面上。 该组合物直接由第一层的表面形成。 附加材料的纳米结构在第一聚合物嵌段内自组装。 同时蚀刻膜和第一层。 纳米结构的蚀刻速率低于嵌段共聚物的蚀刻速率，并且低于第一层的蚀刻速率。 部分电影被删除。 特征保留在第一层的表面上。

公开(公告)号：US20100279062A1

公开(公告)日：2010-11-04

申请号：US12834097

申请日：2010-07-12

Applicant: Dan B. Millward ,  Donald Westmoreland ,  Gurtej Sandhu

Inventor： Dan B. Millward ,  Donald Westmoreland ,  Gurtej Sandhu

IPC: B32B3/30

CPC classification number: H01J37/02 ,  B81C1/00031 ,  B81C2201/0149 ,  B81C2201/0198 ,  B82Y30/00 ,  G03F7/0002 ,  G03F7/265 ,  Y10T428/24 ,  Y10T428/24149 ,  Y10T428/24174 ,  Y10T428/2438

Abstract: Methods for fabricating sublithographic, nanoscale microstructures arrays including openings and linear microchannels utilizing self-assembling block copolymers, and films and devices formed from these methods are provided. In some embodiments, the films can be used as a template or mask to etch openings in an underlying material layer.

Abstract translation: 提供了使用自组装嵌段共聚物制造包括开口和线性微通道的亚光刻纳米尺度微结构阵列的方法，以及由这些方法形成的膜和器件。 在一些实施例中，膜可以用作模板或掩模来蚀刻下层材料层中的开口。

公开(公告)号：US20100169042A1

公开(公告)日：2010-07-01

申请号：US12600527

申请日：2008-04-02

Applicant: Yuki Aritsuka ,  Morihisa Hoga

Inventor： Yuki Aritsuka ,  Morihisa Hoga

IPC: G06F15/00

CPC classification number: G01B21/20 ,  B81C99/0065 ,  B81C2201/0153 ,  B81C2201/0198 ,  G03F1/84

Abstract: A system for measuring a shape, includes an external storage unit storing tolerances of first and second shape factors defining a design shape of a measuring object; a first measuring tool measuring the first shape factor of the measuring object to obtain measurement data; and a measurement processing unit determining a shape of the measuring object. The measurement processing unit includes; a comparison module comparing the measurement data of the first shape factor with the tolerance of the first shape factor; a verification module composing a predicted shape using the measurement data and verifying whether the predicted shape is formed as a figure; a calculation module calculating predicted data of the second shape factor from the predicted shape; and a determination module determining a measurement shape by comparing the predicted data with the tolerance of the second shape factor.

Abstract translation: 一种用于测量形状的系统，包括存储限定测量对象的设计形状的第一和第二形状因子的公差的外部存储单元; 第一测量工具，测量测量对象的第一形状因子以获得测量数据; 以及测量处理单元，确定测量对象的形状。 测量处理单元包括： 将所述第一形状因子的测量数据与所述第一形状系数的公差进行比较的比较模块; 使用所述测量数据构成预测形状的验证模块，并验证所述预测形状是否形成为图形; 计算模块，根据所述预测形状计算所述第二形状因子的预测数据; 以及确定模块，通过将预测数据与第二形状因子的公差进行比较来确定测量形状。

公开(公告)号：US20100093160A1

公开(公告)日：2010-04-15

申请号：US12330898

申请日：2008-12-09

Applicant: Yonghan Roh ,  Kyoungseob Kim ,  Seokwon Jeong ,  Hyungjin Kim ,  Sungha Park

Inventor： Yonghan Roh ,  Kyoungseob Kim ,  Seokwon Jeong ,  Hyungjin Kim ,  Sungha Park

IPC: H01L21/266 ,  H01L21/311

CPC classification number: H01L21/32139 ,  B81C1/00396 ,  B81C2201/0149 ,  B81C2201/0198 ,  B82Y10/00 ,  H01L21/0332 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/78

Abstract: Provided are methods of forming nano-devices. One of the methods includes forming a nano-scale self-assembly material layer on a substrate formed of at least one layer, forming a mask layer on the self-assembly material layer, performing a surface treatment process on the substrate using the mask layer as a mask, and removing the self-assembly material layer.Accordingly, it is possible to fabricate nano-devices through a nano-scale substrate patterning process, ion implantation process and etching process, without using a light source.

Abstract translation: 提供了形成纳米器件的方法。 其中一种方法包括在由至少一层形成的衬底上形成纳米级自组装材料层，在自组装材料层上形成掩模层，使用掩模层在衬底上进行表面处理工艺 掩模，并且去除自组装材料层。 因此，可以通过纳米级基板图案化工艺，离子注入工艺和蚀刻工艺制造纳米器件，而不使用光源。

公开(公告)号：US07559619B2

公开(公告)日：2009-07-14

申请号：US11204648

申请日：2005-08-15

Applicant: Steven E. Ready ,  William S. Wong ,  Scott J. H. Limb

Inventor： Steven E. Ready ,  William S. Wong ,  Scott J. H. Limb

IPC: B41J29/393

CPC classification number: B41J2/2139 ,  B81C99/0065 ,  B81C2201/0184 ,  B81C2201/0198

Abstract: A digital lithography system including a droplet source (printhead) for selectively ejecting liquid droplets of a phase-change masking material, and an imaging system for capturing (generating) image data representing printed features formed by the ejected liquid droplets. The system also includes a digital control system that detects defects in the printed features, for example, by comparing the image data with stored image data. The digital control system then modifies the printed feature to correct the defect, for example, by moving the printhead over the defect and causing the printhead to eject droplets onto the defect's location. In one embodiment, a single-printhead secondary printer operates in conjunction with a multi-printhead main printer to correct defects.

Abstract translation: 一种数字光刻系统，包括用于选择性地喷射相变掩模材料的液滴的液滴源（打印头）和用于捕获（产生）表示喷射液滴形成的打印特征的图像数据的成像系统。 该系统还包括数字控制系统，其检测打印特征中的缺陷，例如通过将图像数据与存储的图像数据进行比较。 然后，数字控制系统修改打印的特征以校正缺陷，例如通过将打印头移动到缺陷上并使打印头将液滴喷射到缺陷的位置上。 在一个实施例中，单打印头二次打印机与多打印头主打印机一起操作以校正缺陷。