公开(公告)号：US08247702B2

公开(公告)日：2012-08-21

申请号：US12702616

申请日：2010-02-09

Applicant: Takuya Kouya

Inventor： Takuya Kouya

IPC: H05K1/16

CPC classification number: H05K1/0204 ,  H01L23/142 ,  H01L24/16 ,  H01L24/29 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2224/2919 ,  H01L2224/29191 ,  H01L2224/29339 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/484 ,  H01L2224/48599 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01068 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/1517 ,  H01L2924/157 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/3011 ,  H01L2924/30111 ,  H05K1/021 ,  H05K3/4682 ,  H05K2201/09054 ,  Y10T428/24917 ,  H01L2924/0715 ,  H01L2924/0665 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/01004 ,  H01L2224/85399 ,  H01L2224/05599

Abstract: An integrated circuit mounted board includes a printed wiring board and an integrated circuit bare chip mounted on the printed wiring board. The printed wiring board includes a metal base, an insulating member made of an insulating material and disposed on the metal base, and a wiring pattern disposed on the insulating member. The wiring pattern includes an electrode part to which the integrated circuit bare chip is electrically coupled. The insulating member includes an under region being opposite to the electrode part. The metal base includes a metal substrate and a metal portion protruding from the metal substrate. The metal portion is buried in the under region of the insulating member.

Abstract translation: 集成电路安装板包括安装在印刷线路板上的印刷线路板和集成电路裸芯片。 印刷布线板包括金属基底，由绝缘材料制成并设置在金属基底上的绝缘构件和布置在绝缘构件上的布线图案。 布线图案包括集成电路裸芯片电耦合到的电极部分。 绝缘构件包括与电极部相对的下部区域。 金属基底包括金属基底和从金属基底突出的金属部分。 金属部分埋在绝缘部件的下部区域。

公开(公告)号：US08236619B2

公开(公告)日：2012-08-07

申请号：US13092913

申请日：2011-04-23

Applicant: Charles W. C. Lin ,  Chia-Chung Wang

Inventor： Charles W. C. Lin ,  Chia-Chung Wang

IPC: H01L21/00

CPC classification number: H01L21/486 ,  H01L23/3677 ,  H01L24/29 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/83 ,  H01L24/85 ,  H01L33/483 ,  H01L33/642 ,  H01L2224/2919 ,  H01L2224/29339 ,  H01L2224/32188 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/83855 ,  H01L2224/85207 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01031 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01058 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/0132 ,  H01L2924/0134 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/12041 ,  H01L2924/15174 ,  H01L2924/16195 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/351 ,  H05K1/0204 ,  H05K1/115 ,  H05K3/0061 ,  H05K3/06 ,  H05K2201/09054 ,  H05K2201/09509 ,  H05K2201/10106 ,  H05K2203/0369 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/01007 ,  H01L2924/01015 ,  H01L2924/01026 ,  H01L2924/00012

Abstract: A method of making a semiconductor chip assembly includes providing a post and a base, mounting a second adhesive on the base, mounting a substrate with a conductive pattern on the second adhesive, mounting a first adhesive on the substrate and mounting a conductive layer on the first adhesive, then flowing the first adhesive upward between the post and the conductive layer and flowing the second adhesive upward between the post and the substrate, solidifying the adhesives, then providing a conductive trace that includes a pad, a terminal, the conductive pattern, first and second vias and a selected portion of the conductive layer, mounting a semiconductor device on the post, wherein a heat spreader includes the post and the base, electrically connecting the semiconductor device to the conductive trace and thermally connecting the semiconductor device to the heat spreader.

Abstract translation: 一种制造半导体芯片组件的方法包括提供柱和基座，将第二粘合剂安装在基座上，将具有导电图案的基板安装在第二粘合剂上，将第一粘合剂安装在基板上并将导电层安装在 第一粘合剂，然后使第一粘合剂在柱和导电层之间向上流动并使第二粘合剂在柱和基底之间向上流动，固化粘合剂，然后提供包括垫，端子，导电图案的导电迹线， 第一和第二通孔和导电层的选定部分，将半导体器件安装在柱上，其中散热器包括柱和基座，将半导体器件电连接到导电迹线并将半导体器件热连接到热 吊具

公开(公告)号：US08232576B1

公开(公告)日：2012-07-31

申请号：US12848175

申请日：2010-08-01

Applicant: Charles W. C. Lin ,  Chia-Chung Wang ,  Sangwhoo Lim

Inventor： Charles W. C. Lin ,  Chia-Chung Wang ,  Sangwhoo Lim

IPC: H01L33/00 ,  H01L23/34

CPC classification number: H01L21/486 ,  H01L21/4882 ,  H01L23/3677 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L33/483 ,  H01L33/62 ,  H01L33/642 ,  H01L2224/29144 ,  H01L2224/32188 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48464 ,  H01L2224/48639 ,  H01L2224/48644 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/83192 ,  H01L2224/83805 ,  H01L2224/83815 ,  H01L2224/85207 ,  H01L2224/85439 ,  H01L2224/85444 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01028 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/01322 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2924/19041 ,  H05K1/0204 ,  H05K1/021 ,  H05K3/0061 ,  H05K2201/09054 ,  H05K2201/09745 ,  H05K2201/10106 ,  H01L2924/0105 ,  H01L2224/32225 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor chip assembly includes a semiconductor device, a heat spreader, a conductive trace and an adhesive. The heat spreader includes a post, a base and a ceramic block. The post extends upwardly from the base into an opening in the adhesive, the base extends laterally from the post and the ceramic block is embedded in the post. The semiconductor device overlaps the ceramic block, is electrically connected to the conductive trace and is thermally connected to the ceramic block. The adhesive extends between the post and the conductive trace and between the base and the conductive trace. The conductive trace provides signal routing between a pad and a terminal.

Abstract translation: 半导体芯片组件包括半导体器件，散热器，导电迹线和粘合剂。 散热器包括柱，基座和陶瓷块。 柱从基部向上延伸到粘合剂中的开口中，基部从柱侧向延伸，并且陶瓷块嵌入柱中。 半导体器件与陶瓷块重叠，电连接到导电迹线并且热连接到陶瓷块。 粘合剂在柱和导电迹线之间以及基部和导电迹线之间延伸。 导电迹线提供焊盘和端子之间的信号路由。

公开(公告)号：US08212149B2

公开(公告)日：2012-07-03

申请号：US12041916

申请日：2008-03-04

Applicant: Sampath Komarapalayam Velayudham Karikalan ,  Rezaur Rahman Khan

Inventor： Sampath Komarapalayam Velayudham Karikalan ,  Rezaur Rahman Khan

IPC: H05K1/00 ,  H05K1/03 ,  H05K1/16

CPC classification number: H05K1/0224 ,  H05K1/024 ,  H05K1/0245 ,  H05K2201/0191 ,  H05K2201/09036 ,  H05K2201/09045 ,  H05K2201/09054 ,  H05K2201/0969 ,  H05K2201/09736 ,  H05K2201/09745 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49147

Abstract: Magnetic field distribution and mutual capacitance control for transmission lines are provided. A first circuit board is fabricated by attaching a reference plane layer to a dielectric material layer, and attaching a first trace to the second surface of the dielectric material. A surface profile of the reference plane layer is modified to decrease a resistance of a return current signal path through the reference plane layer, to reduce a magnetic field coupling between the first trace and a second trace. A second circuit board is fabricated by attaching a reference plane layer to a dielectric material layer, attaching a trace to the dielectric material, and forming a solder mask layer on the dielectric material layer over the trace. An effective dielectric constant of the solder mask layer is modified to reduce or increase a mutual capacitance between the first trace and a second trace on the dielectric material.

Abstract translation: 提供传输线的磁场分布和互电容控制。 通过将参考平面层附着到介电材料层并且将第一迹线附接到电介质材料的第二表面来制造第一电路板。 修改参考平面层的表面轮廓以减小通过参考平面层的返回电流信号路径的电阻，以减小第一迹线和第二迹线之间的磁场耦合。 通过将参考平面层附着到电介质材料层，将迹线附着到电介质材料上，以及在迹线上的介电材料层上形成焊料掩模层来制造第二电路板。 修改焊接掩模层的有效介电常数以减小或增加介电材料上的第一迹线和第二迹线之间的互电容。

公开(公告)号：US08178395B2

公开(公告)日：2012-05-15

申请号：US13113051

申请日：2011-05-22

Applicant: Charles W. C. Lin ,  Chia-Chung Wang ,  Ming Yu Shih

Inventor： Charles W. C. Lin ,  Chia-Chung Wang ,  Ming Yu Shih

IPC: H01L21/60

CPC classification number: H01L21/486 ,  H01L23/3677 ,  H01L24/29 ,  H01L24/45 ,  H01L24/48 ,  H01L24/83 ,  H01L24/85 ,  H01L33/483 ,  H01L33/642 ,  H01L2224/2919 ,  H01L2224/32188 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/83855 ,  H01L2224/85207 ,  H01L2924/00014 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01028 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01058 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/12041 ,  H01L2924/181 ,  H01L2924/19041 ,  H05K1/0204 ,  H05K3/0061 ,  H05K2201/09054 ,  H05K2201/10106 ,  H05K2203/0369 ,  H01L2924/0665 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A method of making a semiconductor chip assembly includes providing a post, a base, a support layer and an underlayer, wherein the post extends above the base and the support layer is sandwiched between the base and the underlayer, mounting an adhesive on the base including inserting the post into an opening in the adhesive, mounting a conductive layer on the adhesive including aligning the post with an aperture in the conductive layer, then flowing the adhesive upward between the post and the conductive layer, solidifying the adhesive, then providing a conductive trace that includes a pad, a terminal and a selected portion of the conductive layer, providing a heat spreader that includes the post, the base, the underlayer and a thermal via that extends from the base through the support layer to the underlayer, then mounting a semiconductor device on the post, electrically connecting the semiconductor device to the conductive trace and thermally connecting the semiconductor device to the heat spreader.

Abstract translation: 一种制造半导体芯片组件的方法包括提供柱，基底，支撑层和底层，其中柱延伸到基底之上，并且支撑层夹在基底和底层之间，将粘合剂安装在基底上，包括 将所述柱插入所述粘合剂的开口中，将导电层安装在所述粘合剂上，包括使所述柱与所述导电层中的孔对准，然后使所述粘合剂在所述柱和所述导电层之间向上流动，使所述粘合剂固化， 轨迹，其包括衬垫，端子和导电层的选定部分，提供包括柱，基底，底层的散热器和从基底穿过支撑层延伸到底层的热通孔，然后安装 在该柱上的半导体器件，将半导体器件电连接到导电迹线并将半导体器件热连接到第二半导体器件 e散热器。

公开(公告)号：US08166643B2

公开(公告)日：2012-05-01

申请号：US12702865

申请日：2010-02-09

Applicant: Kiyoshi Shibata ,  Ryosuke Usui ,  Yasunori Inoue

Inventor： Kiyoshi Shibata ,  Ryosuke Usui ,  Yasunori Inoue

IPC: H05K3/36

CPC classification number: H05K3/445 ,  H01L2224/16 ,  H01L2924/01019 ,  H01L2924/01078 ,  H05K1/056 ,  H05K3/0047 ,  H05K3/44 ,  H05K2201/0382 ,  H05K2201/09054 ,  H05K2201/09609 ,  H05K2201/0969 ,  H05K2203/0323 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49165

Abstract: A method of manufacturing a circuit apparatus includes forming a plurality of pierced holes in a metal substrate. A first wiring layer is formed on one side of the metal substrate via a first insulating layer, and a second wiring layer is formed on the other side of the metal substrate via a second insulating layer. A conductor layer is formed in at least some of the plurality of pierced holes to establish a connection between the first wiring layer and the second wiring layer. A circuit element is connected to the first wiring layer on the one side of the metal substrate. When a plurality of pierced holes are formed, protrusions are formed on a surface of the metal substrate at least along either edge of each of the pierced holes provided with the conductor layer to protrude in a convex manner from the surface of the metal substrate.

Abstract translation: 电路装置的制造方法包括在金属基板上形成多个穿孔。 第一布线层经由第一绝缘层在金属基板的一侧上形成，并且第二布线层经由第二绝缘层形成在金属基板的另一侧上。 在多个穿孔中的至少一些穿孔中形成导体层，以建立第一布线层和第二布线层之间的连接。 电路元件连接到金属基板的一侧上的第一布线层。 当形成多个穿孔时，至少沿着设置有导体层的每个穿孔的任一边缘，在金属基板的表面上形成突起，以从金属基板的表面凸出突出。

公开(公告)号：US20120082420A1

公开(公告)日：2012-04-05

申请号：US13325817

申请日：2011-12-14

Applicant: Shinichi AOKI

Inventor： Shinichi AOKI

IPC: G02B6/36

CPC classification number: G02B6/4269 ,  G02B6/4281 ,  H05K1/0204 ,  H05K1/0206 ,  H05K1/189 ,  H05K3/4046 ,  H05K7/205 ,  H05K2201/066 ,  H05K2201/09054 ,  H05K2201/10689

Abstract: An optical module includes: a flexible board having a first surface on which a component is mounted and a second surface opposite to the first surface; a bottom electrode part having a bottom surface on which a heat release electrode is provided, the bottom electrode part mounted on the first surface of the flexible board; and a heat release member configured to absorb heat from the bottom electrode part and release the heat to outside. The heat release member is arranged close to said second surface of the flexible board at a position where the bottom electrode part is mounted.

Abstract translation: 光学模块包括：柔性板，其具有安装有部件的第一表面和与第一表面相对的第二表面; 具有底面的底部电极部分，其上设置有放热电极，所述底部电极部分安装在所述柔性板的第一表面上; 以及散热构件，其构造成从底部电极部吸收热量并将热量释放到外部。 散热构件在安装底部电极部分的位置处靠近柔性板的第二表面设置。

公开(公告)号：US08129742B2

公开(公告)日：2012-03-06

申请号：US13078928

申请日：2011-04-02

Applicant: Charles W. C. Lin ,  Chia-Chung Wang

Inventor： Charles W. C. Lin ,  Chia-Chung Wang

IPC: H01L33/00 ,  H01L23/367

CPC classification number: H01L21/486 ,  H01L23/3677 ,  H01L24/16 ,  H01L24/29 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/83 ,  H01L24/85 ,  H01L33/483 ,  H01L33/642 ,  H01L2224/2919 ,  H01L2224/29339 ,  H01L2224/32188 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/83855 ,  H01L2224/85207 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01028 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01058 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/12041 ,  H01L2924/16195 ,  H01L2924/181 ,  H01L2924/19041 ,  H05K1/0204 ,  H05K3/0061 ,  H05K2201/09054 ,  H05K2201/10106 ,  H05K2203/0369 ,  H01L2924/00014 ,  H01L2924/0665 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor chip assembly includes a semiconductor device, a heat spreader, a conductive trace and an adhesive. The heat spreader includes a post and a base. The conductive trace includes a pad, a terminal and a plated through-hole. The semiconductor device is electrically connected to the conductive trace and thermally connected to the heat spreader. The post extends upwardly from the base into an opening in the adhesive, and the base extends laterally from the post. The conductive trace provides signal routing between the pad and the terminal using the plated through-hole.

Abstract translation: 半导体芯片组件包括半导体器件，散热器，导电迹线和粘合剂。 散热器包括一个柱子和一个底座。 导电迹线包括焊盘，端子和电镀通孔。 半导体器件电连接到导电迹线并热连接到散热器。 柱从基部向上延伸到粘合剂中的开口中，并且基部从柱横向延伸。 导电迹线使用电镀通孔在焊盘和端子之间提供信号路由。

公开(公告)号：US08071998B2

公开(公告)日：2011-12-06

申请号：US12325661

申请日：2008-12-01

Applicant: Kuei-Fang Chen

Inventor： Kuei-Fang Chen

IPC: H01L33/00

CPC classification number: F21V29/51 ,  F21K9/00 ,  F21V29/505 ,  F21V29/763 ,  F21V29/773 ,  F21Y2115/10 ,  H05K1/0204 ,  H05K2201/09054 ,  H05K2201/10106 ,  H05K2201/10416

Abstract: A light emitting assembly includes: a heat sink having a base wall and at least one mesa protruding from the base wall; and at least one light emitting package unit having at least one light emitting package bonded to the mesa so as to transfer heat generated from the light emitting package to the base wall through the mesa. A circuit board includes a substrate that is formed with at least one through-hole, and is provided with a conductive contact unit that is formed on the substrate. The heat sink is attached to the substrate such that the mesa protrudes from the base wall into and through the through-hole in the substrate so as to be bonded to the light emitting package.

Abstract translation: 发光组件包括：散热器，具有底壁和从底壁突出的至少一个台面; 以及至少一个具有至少一个发光封装的发光封装单元，其结合到所述台面以便将从所述发光封装产生的热量通过所述台面传递到所述基壁。 电路板包括形成有至少一个通孔的基板，并且设置有形成在基板上的导电接触单元。 散热器附接到基板，使得台面从基壁突出到基板中并穿过基板中的通孔，以便结合到发光封装。

公开(公告)号：US20110278638A1

公开(公告)日：2011-11-17

申请号：US13192463

申请日：2011-07-28

Applicant: Charles W.C. Lin ,  Chia-Chung Wang

Inventor： Charles W.C. Lin ,  Chia-Chung Wang

IPC: H01L33/62

CPC classification number: H01L21/486 ,  H01L23/3677 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/83 ,  H01L24/85 ,  H01L33/483 ,  H01L33/642 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29339 ,  H01L2224/32188 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48227 ,  H01L2224/48639 ,  H01L2224/73265 ,  H01L2224/83855 ,  H01L2224/85207 ,  H01L2224/85439 ,  H01L2224/92 ,  H01L2224/92247 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01058 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/0134 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/351 ,  H05K1/0204 ,  H05K3/0061 ,  H05K2201/09054 ,  H05K2201/10106 ,  H05K2203/0369 ,  H01L2924/00014 ,  H01L2924/0665 ,  H01L2924/01007 ,  H01L2924/01031 ,  H01L2924/01015 ,  H01L2924/01047 ,  H01L2924/01026 ,  H01L2924/0104 ,  H01L2924/01033 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor chip assembly includes a semiconductor device, a heat spreader, a conductive trace and first and second adhesives. The heat spreader includes a first post, a second post and a dielectric base. The conductive trace includes a pad and a terminal. The semiconductor device is electrically connected to the conductive trace and thermally connected to the heat spreader. The first post extends from the dielectric base in a first vertical direction into a first opening in the first adhesive, the second post extends from the dielectric base in a second vertical direction into a second opening in the second adhesive and the dielectric base contacts and is sandwiched between and extends laterally from the posts. The conductive trace provides signal routing between the pad and the terminal.

Abstract translation: 半导体芯片组件包括半导体器件，散热器，导电迹线以及第一和第二粘合剂。 散热器包括第一柱，第二柱和电介质基底。 导电迹线包括焊盘和端子。 半导体器件电连接到导电迹线并热连接到散热器。 第一柱从第一垂直方向的电介质基底延伸到第一粘合剂中的第一开口中，第二柱从第二垂直方向的电介质基底延伸到第二粘合剂中的第二开口中，并且电介质基底接触并且是 夹在柱之间并横向延伸。 导电迹线提供焊盘和端子之间的信号路由。