Array antenna and radar apparatus
    1.
    发明申请
    Array antenna and radar apparatus 有权
    阵列天线和雷达设备

    公开(公告)号:US20100238067A1

    公开(公告)日:2010-09-23

    申请号:US12661383

    申请日:2010-03-16

    CPC classification number: H01Q21/08 H01Q13/206 H01Q21/0075

    Abstract: The array antenna includes a feed line, and a plurality of radiating element sections arranged at a predetermined arranging interval in a first direction, each of the radiating element sections including at least one radiating element fed a traveling wave through the feed line. The inter-element line length as a length of the feed line between each succeeding two of the radiating element sections is longer than the arranging interval in the first direction.

    Abstract translation: 阵列天线包括馈电线,以及以第一方向以预定的布置间隔布置的多个辐射元件部分,每个辐射元件部分包括馈送通过馈电线的行波的至少一个辐射元件。 作为每个后续的两个辐射元件部分之间的馈送线的长度的元件间线长度比第一方向上的布置间隔长。

    Array antenna and radar apparatus
    2.
    发明授权
    Array antenna and radar apparatus 有权
    阵列天线和雷达设备

    公开(公告)号:US08471775B2

    公开(公告)日:2013-06-25

    申请号:US12661383

    申请日:2010-03-16

    CPC classification number: H01Q21/08 H01Q13/206 H01Q21/0075

    Abstract: The array antenna includes a feed line, and a plurality of radiating element sections arranged at a predetermined arranging interval in a first direction, each of the radiating element sections including at least one radiating element fed a traveling wave through the feed line. The inter-element line length as a length of the feed line between each succeeding two of the radiating element sections is longer than the arranging interval in the first direction.

    Abstract translation: 阵列天线包括馈电线,以及以第一方向以预定的布置间隔布置的多个辐射元件部分,每个辐射元件部分包括馈送通过馈电线的行波的至少一个辐射元件。 作为每个后续的两个辐射元件部分之间的馈送线的长度的元件间线长度比第一方向上的布置间隔长。

    Semiconductor wafer etching process and semiconductor device
    6.
    发明授权
    Semiconductor wafer etching process and semiconductor device 失效
    半导体晶片蚀刻工艺和半导体器件

    公开(公告)号:US5843849A

    公开(公告)日:1998-12-01

    申请号:US662632

    申请日:1996-06-13

    CPC classification number: H01L29/66462 H01L21/30612 H01L29/7783

    Abstract: A first semiconductor layer and a second semiconductor layer are laminated on a semiconductor wafer in that order. A resist pattern having an opening is formed on the second semiconductor layer. The second semiconductor layer is etched through the opening in the formed resist pattern to expose the first semiconductor layer. A surface oxide film is formed on the exposed surface of the first semiconductor layer and then selectively etched away. Alternatively, the exposed surface of the first semiconductor layer is subjected to a separate oxidization treatment and the resulting surface oxide film is selectively removed in the subsequent etching.

    Abstract translation: 依次层叠在半导体晶片上的第一半导体层和第二半导体层。 具有开口的抗蚀剂图案形成在第二半导体层上。 通过形成的抗蚀图案中的开口蚀刻第二半导体层以暴露第一半导体层。 在第一半导体层的暴露表面上形成表面氧化膜,然后选择性地蚀刻掉。 或者,对第一半导体层的暴露表面进行单独的氧化处理,并在随后的蚀刻中选择性地除去所得的表面氧化膜。

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