公开(公告)号：US20050184371A1

公开(公告)日：2005-08-25

申请号：US10838433

申请日：2004-05-03

Applicant: Chih-An Yang

Inventor： Chih-An Yang

IPC: H01L21/44 ,  H01L21/60 ,  H01L23/498 ,  H05K3/34

CPC classification number: H01L24/81 ,  H01L23/49816 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/81801 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/19043 ,  H05K3/3436 ,  H05K3/3452 ,  H05K3/3484 ,  H05K2201/09845 ,  H05K2201/099 ,  H05K2201/10992 ,  H05K2203/0594 ,  Y02P70/613 ,  H01L2924/00014 ,  H01L2224/05552

Abstract: The present invention provides a circuit carrier for connecting to at least a bump. The circuit carrier comprises a substrate, at least a contact pad on a surface of the substrate and a solder mask layer covering the substrate. The solder mask has at least a stepped opening that exposes a portion of the contact pad. The stepped opening includes at least a first opening and a second opening and the size of the first opening is larger than that of the second opening. The stepped opening of the solder mask layer can contain more pre-solder paste, thus increasing the bonding strength between the bump and the contact pad.

Abstract translation: 本发明提供一种用于连接至少一个凸块的电路载体。 电路载体包括衬底，至少衬底表面上的接触焊盘和覆盖衬底的焊接掩模层。 焊接掩模具有暴露接触焊盘的一部分的至少一个阶梯式开口。 阶梯式开口至少包括第一开口和第二开口，并且第一开口的尺寸大于第二开口的大小。 焊接掩模层的阶梯式开口可以包含更多的预焊膏，从而增加凸块和接触垫之间的结合强度。

公开(公告)号：US20050173151A1

公开(公告)日：2005-08-11

申请号：US10774115

申请日：2004-02-06

Applicant: Glen Shepherd ,  Anthony Burton ,  Michael Ng ,  Mimi Tantillo ,  Dieu-Huong Tran

Inventor： Glen Shepherd ,  Anthony Burton ,  Michael Ng ,  Mimi Tantillo ,  Dieu-Huong Tran

IPC: H05K1/11 ,  H05K3/34 ,  H05K1/18

CPC classification number: H05K1/115 ,  H05K1/114 ,  H05K3/3442 ,  H05K3/3452 ,  H05K2201/09381 ,  H05K2201/099 ,  H05K2201/10636 ,  Y02P70/611 ,  Y02P70/613 ,  Y10T29/49144 ,  Y10T29/49165

Abstract: This invention relates to a substrate with via and pad structure(s) to reduce solder wicking. Each via and pad structure connects a component to conductive layers associated with the substrate. The substrate includes one or more plated vias, solder mask(s) surrounding the plated vias, and a conductive pad with a conductive trace connected to each plated via. The conductive pad extends beyond the terminal sides to increase solder formation and the solder mask reduces solder formation at the terminal end of the component. The via and pad structure is suitable for a variety of components and high component density. The invention also provides a computer implemented method for calculating the maximum distance of a conductive pad extending beyond the terminal side of a component.

Abstract translation: 本发明涉及一种具有通孔和衬垫结构以减少焊料芯吸的衬底。 每个通孔和焊盘结构将组件连接到与衬底相关联的导电层。 衬底包括一个或多个电镀通孔，围绕镀覆通孔的焊接掩模，以及具有连接到每个电镀通孔的导电迹线的导电焊盘。 导电焊盘延伸超过端子侧以增加焊料形成，并且焊接掩模减少部件终端处的焊料形成。 通孔和焊盘结构适用于各种组件和高组件密度。 本发明还提供一种用于计算延伸超过部件的端子侧的导电焊盘的最大距离的计算机实现的方法。

公开(公告)号：US20050077079A1

公开(公告)日：2005-04-14

申请号：US10967290

申请日：2004-10-19

Applicant: Mitsuo Suehiro

Inventor： Mitsuo Suehiro

IPC: H01R4/02 ,  H01L21/60 ,  H05K1/18 ,  H05K3/28 ,  H05K3/34 ,  H05K1/00

CPC classification number: H01L24/81 ,  H01L24/98 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/11334 ,  H01L2224/13021 ,  H01L2224/16237 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81136 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81385 ,  H01L2224/81801 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/15787 ,  H05K3/281 ,  H05K3/3436 ,  H05K3/3452 ,  H05K2201/099 ,  H05K2201/2036 ,  H05K2203/0182 ,  H05K2203/0191 ,  H05K2203/0264 ,  H05K2203/176 ,  Y02P70/613 ,  Y10T29/49144 ,  Y10T29/49147 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A printed circuit board unit comprises an insulated film disposed between a printed circuit board and an electronic component so as to define a through hole for receiving the solder bump. The through hole may be designed to form a constriction in the solder bump. Electric connection can reliably be established between the printed circuit board and the electronic component since the solder bump is allowed to penetrate through the through hole in the insulated film. When the insulated film is brought away from the printed circuit board, the insulated film serves to tear the solder bump in two pieces at the constriction, so that the electronic component can easily be detached from the printed circuit board.

Abstract translation: 印刷电路板单元包括布置在印刷电路板和电子部件之间的绝缘膜，以便限定用于接收焊料凸块的通孔。 通孔可以设计成在焊料凸块中形成收缩。 由于允许焊料凸块穿过绝缘膜中的通孔，所以能够可靠地在印刷电路板和电子部件之间建立电连接。 当绝缘膜离开印刷电路板时，绝缘膜用于在缩小时将焊料凸块撕成两片，使得电子部件可以容易地从印刷电路板上拆下。

公开(公告)号：US06858806B2

公开(公告)日：2005-02-22

申请号：US10043002

申请日：2002-01-09

Applicant: Antonio Canova

Inventor： Antonio Canova

IPC: H05K1/02 ,  H05K3/30 ,  H05K3/34 ,  H05K1/00

CPC classification number: H05K3/305 ,  H05K1/0263 ,  H05K3/341 ,  H05K3/3452 ,  H05K2201/099 ,  H05K2201/10272 ,  H05K2201/1028 ,  H05K2201/1084 ,  H05K2203/0588 ,  Y02P70/613 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/53178

Abstract: There is described a process for producing printed circuits comprising a laminar support, an electrically conductive track on the laminar support, and an auxiliary conductive element soldered to the conductive track. There is a provision to apply the auxiliary conductive element by means of an apparatus for applying SMD components.

Abstract translation: 描述了一种用于生产印刷电路的方法，该印刷电路包括层状载体，层状载体上的导电轨道和焊接到导电轨道的辅助导电元件。 通过用于施加SMD部件的装置来施加辅助导电元件。

公开(公告)号：US20050013978A1

公开(公告)日：2005-01-20

申请号：US10919342

申请日：2004-08-17

Applicant: Hiromi Honda ,  Yasushi Takeuchi

Inventor： Hiromi Honda ,  Yasushi Takeuchi

IPC: H05K3/34 ,  B32B3/00

CPC classification number: H05K3/3452 ,  H05K3/3447 ,  H05K3/3463 ,  H05K2201/0989 ,  H05K2201/099 ,  H05K2201/09909 ,  H05K2201/2081 ,  H05K2203/0315 ,  Y10T428/24917

Abstract: A printed wiring board is provided in which lift-off and land peeling do not occur during soldering of an inserted component onto the printed wiring board, and hence pattern breakage does not occur, but with no increase in cost. A plurality of lands 6 are each formed continuously across surfaces of a substrate and an inner peripheral surface of one of a plurality of soldering through holes 5 into which leads 2 of an inserted component 3 to be mounted onto the printed wiring board are inserted before soldering is carried out, and a solder resist 8 is coated onto the lands 6.

Abstract translation: 提供了一种印刷电路板，其中在将插入的部件焊接到印刷电路板上时不会发生剥离和剥离，因此不会发生图案破损，而不增加成本。 多个焊盘6分别连续地形成在焊接的基板的表面和多个焊接通孔5的内周面之间，焊接前的插入部件3的引线2插入到印刷线路板上 并且将焊料抗蚀剂8涂覆到焊盘6上。

公开(公告)号：US20040172819A1

公开(公告)日：2004-09-09

申请号：US10758698

申请日：2004-01-15

Inventor： Fumiaki Karasawa

IPC: H05K003/02 ,  H05K003/10

CPC classification number: H05K3/3452 ,  H01L21/486 ,  H01L23/49838 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16237 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H05K1/111 ,  H05K3/243 ,  H05K2201/09381 ,  H05K2201/0989 ,  H05K2201/099 ,  H05K2201/10674 ,  Y10T29/49155 ,  H01L2224/05599

Abstract: A method of manufacturing a wiring board is provided. The method includes performing a plating process to a land, in a condition that a resist film having an opening for exposing at least the center of the land is formed on a substrate with wires having the land formed thereon, so that a fist portion of an edge of the opening is disposed on the substrate and a second portion of the edge is disposed on the land.

Abstract translation: 提供一种制造布线板的方法。 该方法包括：在具有在其上形成有焊盘的导线的基板上形成至少具有用于露出焊盘的中心的开口的抗蚀剂膜的情况下，对焊盘进行电镀处理，使得第一部分 开口的边缘设置在基板上，边缘的第二部分设置在平台上。

公开(公告)号：US06784556B2

公开(公告)日：2004-08-31

申请号：US10126328

申请日：2002-04-19

Applicant: Paul T. Lin

Inventor： Paul T. Lin

IPC: H01L2348

CPC classification number: H01L24/05 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48465 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/48647 ,  H01L2224/48724 ,  H01L2224/48744 ,  H01L2224/48747 ,  H01L2224/85205 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H05K1/0268 ,  H05K3/3452 ,  H05K2201/099 ,  H05K2203/049 ,  H01L2924/00014 ,  H01L2924/00

Abstract: The present invention provides a solution to the problem of weakening bond integrity in integrated circuit devices due in part to test probes galling and weakening the interconnect pads during functional and reliability test probing. In doing so, the invention enables a lowering of the chance a bond wire or interconnect pad will be lifted during a wire bonding process or in normal operation of an integrated circuit device.

Abstract translation: 本发明提供了解决集成电路器件中的键合完整性弱的问题，部分原因在于在功能和可靠性测试探测期间测试探针磨损和弱化互连焊盘。 在这样做时，本发明能够降低接合线或互连焊盘在引线接合过程期间或在集成电路器件的正常操作中被提升的机会。

公开(公告)号：US06764937B1

公开(公告)日：2004-07-20

申请号：US10385487

申请日：2003-03-12

Applicant: Hubert Allen Vander Plas ,  Frank Berauer

Inventor： Hubert Allen Vander Plas ,  Frank Berauer

IPC: H01L244

CPC classification number: H05K3/3484 ,  H01L24/11 ,  H01L24/13 ,  H01L29/0657 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2924/0001 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10157 ,  H05K3/3452 ,  H05K3/403 ,  H05K2201/09154 ,  H05K2201/099 ,  H05K2203/0568 ,  H05K2203/1394 ,  H01L2224/0401

Abstract: A method for depositing a solder layer or solder bump on a sloped surface. The method includes etching a sloped surface on a planar semiconductor substrate, depositing a solder-wettable layer on the sloped surface, masking the wettabler layer with a coating layer to control the position of the solder deposition, and using an organic film to prevent the solder from being deposited at regions not above either the wettable layer or the coating layer. Also, a semiconductor device structure on which a solder layer or solder bump is formed exclusively on a sloped surface.

Abstract translation: 一种用于在倾斜表面上沉积焊料层或焊料凸块的方法。 该方法包括蚀刻平面半导体衬底上的倾斜表面，在倾斜表面上沉积焊料可润湿层，用涂层掩蔽湿润层以控制焊料沉积的位置，并使用有机膜防止焊料 不会沉积在可湿性层或涂层之上的区域。 此外，其中仅在倾斜表面上形成焊料层或焊料凸块的半导体器件结构。

公开(公告)号：US20040099936A1

公开(公告)日：2004-05-27

申请号：US10717946

申请日：2003-11-20

Inventor： David V. Caletka ,  Eric A. Johnson

IPC: H01L021/44 ,  H01L023/02 ,  H01L023/52 ,  H01L029/40

CPC classification number: H01L23/50 ,  H01L23/3128 ,  H01L23/49816 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2924/15311 ,  H05K3/3436 ,  H05K3/3452 ,  H05K2201/0989 ,  H05K2201/099 ,  H05K2201/10734 ,  H01L2224/29099 ,  H01L2924/0001

Abstract: A Ball Grid Array package having an increased fatigue life and improved conductive pad adhesion strength, as well as providing sufficient wiring space within the package, is disclosed. In particular, solder joints having a combination of mask-defined and pad-defined solder joint profiles are formed using a mask having non-circular elongated openings. The non-circular elongated openings of the mask have a major axis and a minor axis, such that the dimension of the openings along the major axis is greater than the diameter of the conductive pads, and the dimension of the openings along the minor axis is less than the diameter of the conductive pads. In addition, the major axis of the openings within the mask are selectively oriented in the direction of highest stress for each solder joint within the package, while providing ample wiring space therein.

公开(公告)号：US06734570B1

公开(公告)日：2004-05-11

申请号：US10350851

申请日：2003-01-24

Applicant: John Archer

Inventor： John Archer

IPC: H01L2348

CPC classification number: H01L23/49811 ,  H01L23/49838 ,  H01L23/50 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/056 ,  H01L2224/16 ,  H05K1/111 ,  H05K3/3452 ,  H05K3/3484 ,  H05K2201/09381 ,  H05K2201/09709 ,  H05K2201/099 ,  H05K2201/10674 ,  H05K2203/0545 ,  Y02P70/611 ,  H01L2924/00014

Abstract: A method of fabricating a solder bumped substrate for a flip-chip integrated circuit (IC) package is provided. The method includes the following steps. Providing a substrate material. Patterning a conductive layer on the substrate material that includes a plurality of circuit traces coupled to a plurality of bonding pads, wherein the bonding pads are arranged to correspond to input/output (I/O) pads on the flip-chip IC. Fabricating a solder mask layer over the conductive layer, wherein the solder mask layer defines a pad opening corresponding to each of the bonding pads, and wherein the pad openings defined by the solder mask layer are tapered such that each pad opening includes an expanded end and a tapered end. Printing solder onto a portion of each bonding pad that is exposed by the expanded end of the corresponding pad opening. Reflowing the printed solder to form solder bumps on each bonding pad.

Abstract translation: 提供一种制造用于倒装芯片集成电路（IC）封装的焊料凸起衬底的方法。 该方法包括以下步骤。 提供衬底材料。 对包括耦合到多个接合焊盘的多个电路迹线的衬底材料上的导电层进行构图，其中所述接合焊盘被布置为对应于所述倒装芯片IC上的输入/输出（I / O）焊盘。 在导电层上制造焊接掩模层，其中焊料掩模层限定对应于每个焊盘的焊盘开口，并且其中由焊料掩模层限定的焊盘开口是锥形的，使得每个焊盘开口包括扩展端和 锥形端。 将焊料印刷到由相应的焊盘开口的扩展端露出的每个焊盘的一部分上。 回填印刷的焊料，以在每个焊盘上形成焊料凸块。