公开(公告)号：US10159148B2

公开(公告)日：2018-12-18

申请号：US15700483

申请日：2017-09-11

Applicant: Invensas Corporation

Inventor： Rajesh Katkar ,  Cyprian Emeka Uzoh ,  Belgacem Haba ,  Ilyas Mohammed

IPC: H05K1/09 ,  H05K1/03 ,  H05K1/11 ,  H01L23/498 ,  H01L21/48 ,  H01L23/13 ,  H05K3/40 ,  H05K3/42 ,  H01L23/373 ,  H01L23/538 ,  H01L23/00 ,  H01L25/065

Abstract: Interposers and methods of making the same are disclosed herein. In one embodiment, an interposer includes a region having first and second oppositely facing surfaces and a plurality of pores, each pore extending in a first direction from the first surface towards the second surface, wherein alumina extends along a wall of each pore; a plurality of electrically conductive connection elements extending in the first direction, consisting essentially of aluminum and being electrically isolated from one another by at least the alumina; a first conductive path provided at the first surface for connection with a first component external to the interposer; and a second conductive path provided at the second surface for connection with a second component external to the interposer, wherein the first and second conductive paths are electrically connected through at least some of the connection elements.

公开(公告)号：US20180337118A1

公开(公告)日：2018-11-22

申请号：US16017010

申请日：2018-06-25

Applicant: Invensas Corporation

Inventor： Hong Shen ,  Liang Wang ,  Gabriel Z. Guevara ,  Rajesh Katkar ,  Cyprian Emeka Uzoh ,  Laura Wills Mirkarimi

IPC: H01L23/498 ,  H01L25/00 ,  H01L21/48 ,  H01L23/00 ,  H01L25/065

Abstract: An interposer (110) has contact pads at the top and/or bottom surfaces for connection to circuit modules (e.g. ICs 112). The interposer includes a substrate made of multiple layers (110.i). Each layer can be a substrate (110S), possibly a ceramic substrate, with circuitry. The substrates extend vertically. Multiple interposers are fabricated in a single structure (310) made of vertical layers (310.i) corresponding to the interposers' layers. The structure is diced along horizontal planes (314) to provide the interposers. An interposer's vertical conductive lines (similar to through-substrate vias) can be formed on the substrates' surfaces before dicing and before all the substrates are attached to each other. Thus, there is no need to make through-substrate holes for the vertical conductive lines. Non-vertical features can also be formed on the substrates' surfaces before the substrates are attached to each other. Other embodiments are also provided.

公开(公告)号：US20180295718A1

公开(公告)日：2018-10-11

申请号：US16007410

申请日：2018-06-13

Applicant: Invensas Corporation

Inventor： Cyprian Emeka Uzoh ,  Craig Mitchell ,  Belgacem Haba ,  Ilyas Mohammed

IPC: H05K1/02 ,  H01L23/498 ,  H01R12/71 ,  H05K3/42 ,  H05K1/11

CPC classification number: H05K1/0271 ,  H01L23/49827 ,  H01L2924/0002 ,  H01R12/714 ,  H05K1/114 ,  H05K1/115 ,  H05K3/42 ,  H05K2201/09645 ,  H05K2201/10378 ,  H05K2203/0242 ,  H05K2203/025 ,  Y10T29/49165 ,  H01L2924/00

Abstract: A method for making an interconnection component includes forming a mask layer that covers a first opening in a sheet-like element that includes a first opening extending between the first and second surfaces of the element. The element consists essentially of a material having a coefficient of thermal expansion of less than 10 parts per million per degree Celsius. The first opening includes a central opening and a plurality of peripheral openings open to the central opening that extends in an axial direction of the central opening. A conductive seed layer can cover an interior surface of the first opening. The method further includes forming a first mask opening in at least a portion of the mask layer overlying the first opening to expose portions of the conductive seed layer within the peripheral openings; and forming electrical conductors on exposed portions of the conductive seed layer.

公开(公告)号：US20180219001A1

公开(公告)日：2018-08-02

申请号：US15927494

申请日：2018-03-21

Applicant: Invensas Corporation

Inventor： Guilian Gao ,  Charles G. Woychik ,  Cyprian Emeka Uzoh ,  Liang Wang

IPC: H01L25/065 ,  H01L23/367 ,  H01L25/00 ,  H01L23/00 ,  H01L23/373 ,  H01L23/36

Abstract: A device with thermal control is presented. In some embodiments, the device includes a plurality of die positioned in a stack, each die including a chip, interconnects through a thickness of the chip, metal features of electrically conductive composition connected to the interconnects on a bottom side of the chip, and adhesive or underfill layer on the bottom side of the chip. At least one thermally conducting layer, which can be a pyrolytic graphite layer, a layer formed of carbon nanotubes, or a graphene layer, is coupled between a top side of one of the plurality of die and a bottom side of an adjoining die in the stack. A heat sink can be coupled to the thermally conducting layer.

公开(公告)号：US09947618B2

公开(公告)日：2018-04-17

申请号：US15619160

申请日：2017-06-09

Applicant: Invensas Corporation

Inventor： Cyprian Emeka Uzoh ,  Charles G. Woychik ,  Arkalgud R. Sitaram ,  Hong Shen ,  Zhuowen Sun ,  Liang Wang ,  Guilian Gao

IPC: H01L23/04 ,  H01L23/52 ,  H01L21/44 ,  H01L23/522 ,  H01L49/02 ,  H01L21/768 ,  H01L21/8234

CPC classification number: H01L23/5223 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/823431 ,  H01L21/823475 ,  H01L23/5226 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In a microelectronic component having conductive vias (114) passing through a substrate (104) and protruding above the substrate, conductive features (120E.A, 120E.B) are provided above the substrate that wrap around the conductive vias' protrusions (114′) to form capacitors, electromagnetic shields, and possibly other elements. Other features and embodiments are also provided.

公开(公告)号：US09905537B2

公开(公告)日：2018-02-27

申请号：US15360073

申请日：2016-11-23

Applicant: Invensas Corporation

Inventor： Cyprian Emeka Uzoh

IPC: H01L23/48 ,  H01L25/065 ,  H01L23/00 ,  H01L23/522 ,  H01L23/498 ,  H01L21/48 ,  H01L23/538 ,  H01L25/00 ,  H01L21/768 ,  H01L23/14

CPC classification number: H01L25/0657 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/76898 ,  H01L23/147 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/5226 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/02 ,  H01L24/18 ,  H01L24/42 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/85 ,  H01L25/0652 ,  H01L25/50 ,  H01L2224/02372 ,  H01L2224/02373 ,  H01L2224/05599 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/4911 ,  H01L2224/49113 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06548 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012

Abstract: A method of forming a semiconductor package includes providing a substrate having one or more conductive elements disposed therein. Each conductive element extends from a first surface of the substrate toward a second surface of the substrate extending beyond the second surface. The second surface comprises one or more substrate regions not occupied by a conductive element. A first die is attached within a substrate region, and the first die is coupled to at least one of the conductive elements. The first die may be coupled to at least one of the conductive elements by a wire bond connection. Alternatively, an RDL is formed over the second surface, and the first die is coupled to at least one conductive element through the RDL. A second die may be attached to an outer surface of the RDL, and the second die is electrically coupled to the first die through the RDL.

公开(公告)号：US09888584B2

公开(公告)日：2018-02-06

申请号：US14942781

申请日：2015-11-16

Applicant: Invensas Corporation

Inventor： Liang Wang ,  Rajesh Katkar ,  Hong Shen ,  Cyprian Emeka Uzoh

IPC: H05K1/11 ,  H01L23/00 ,  H05K3/40 ,  H05K3/34

CPC classification number: H05K3/4007 ,  H01L24/81 ,  H01L2224/81193 ,  H01L2924/3841 ,  H05K1/111 ,  H05K3/3431

Abstract: A contact pad includes a solder-wettable porous network (310) which wicks the molten solder (130) and thus restricts the lateral spread of the solder, thus preventing solder bridging between adjacent contact pads.

公开(公告)号：US20170374738A1

公开(公告)日：2017-12-28

申请号：US15682049

申请日：2017-08-21

Applicant: Invensas Corporation

Inventor： Bong-Sub Lee ,  Cyprian Emeka Uzoh ,  Charles G. Woychik ,  Liang Wang ,  Laura Wills Mirkarimi ,  Arkalgud R. Sitaram

IPC: H05K1/09 ,  H01L23/498 ,  H01L21/48 ,  H05K1/11

CPC classification number: H05K1/097 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/4867 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L2224/16225 ,  H01L2924/0002 ,  H01L2924/15192 ,  H01L2924/15311 ,  H05K1/112 ,  H05K1/113 ,  H05K1/165 ,  H05K3/188 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/5313 ,  H01L2924/00

Abstract: Interposer circuitry (130) is formed on a possibly sacrificial substrate (210) from a porous core (130′) covered by a conductive coating (130″) which increases electrical conductance. The core is printed from nanoparticle ink. Then a support (120S) is formed, e.g. by molding, to mechanically stabilize the circuitry. A magnetic field can be used to stabilize the circuitry while the circuitry or the support are being formed. Other features are also provided.

公开(公告)号：US20170372994A1

公开(公告)日：2017-12-28

申请号：US15700483

申请日：2017-09-11

Applicant: Invensas Corporation

Inventor： Rajesh Katkar ,  Cyprian Emeka Uzoh ,  Belgacem Haba ,  Ilyas Mohammed

IPC: H01L23/498 ,  H01L25/065 ,  H01L23/373 ,  H01L23/538 ,  H01L23/00 ,  H01L21/48

CPC classification number: H05K1/0306 ,  H01L21/481 ,  H01L21/4853 ,  H01L21/486 ,  H01L23/13 ,  H01L23/3731 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/5381 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/17 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2224/16113 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2225/06589 ,  H01L2225/1023 ,  H01L2225/107 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15331 ,  H05K1/09 ,  H05K1/112 ,  H05K1/115 ,  H05K3/4007 ,  H05K3/42 ,  H05K2201/09545 ,  H05K2201/10378 ,  H05K2203/0323

Abstract: Interposers and methods of making the same are disclosed herein. In one embodiment, an interposer includes a region having first and second oppositely facing surfaces and a plurality of pores, each pore extending in a first direction from the first surface towards the second surface, wherein alumina extends along a wall of each pore; a plurality of electrically conductive connection elements extending in the first direction, consisting essentially of aluminum and being electrically isolated from one another by at least the alumina; a first conductive path provided at the first surface for connection with a first component external to the interposer; and a second conductive path provided at the second surface for connection with a second component external to the interposer, wherein the first and second conductive paths are electrically connected through at least some of the connection elements.

公开(公告)号：US09852969B2

公开(公告)日：2017-12-26

申请号：US15191333

申请日：2016-06-23

Applicant: Invensas Corporation

Inventor： Cyprian Emeka Uzoh ,  Rajesh Katkar

IPC: H01L23/498 ,  H01L23/36 ,  H01L25/065 ,  H01L23/00

CPC classification number: H01L23/49816 ,  H01L23/36 ,  H01L23/49811 ,  H01L24/10 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13169 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/1703 ,  H01L2224/1718 ,  H01L2224/32145 ,  H01L2224/45147 ,  H01L2224/4823 ,  H01L2224/48247 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81825 ,  H01L2224/97 ,  H01L2225/06506 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/15192 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207

Abstract: An apparatus relating generally to a die stack is disclosed. In such an apparatus, a substrate is included. A first bond via array includes first wires each of a first length extending from a first surface of the substrate. An array of bump interconnects is disposed on the first surface. A die is interconnected to the substrate via the array of bump interconnects. A second bond via array includes second wires each of a second length different than the first length extending from a second surface of the die.