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    DIRECT-BONDED LED ARRAYS AND APPLICATIONS
    101.
    发明申请
    DIRECT-BONDED LED ARRAYS AND APPLICATIONS 有权

    公开(公告)号：US20210288037A1

    公开(公告)日：2021-09-16

    申请号：US17327169

    申请日：2021-05-21

    Applicant: Invensas Corporation

    Inventor： Min Tao ,  Liang Wang ,  Rajesh Katkar ,  Cyprian Emeka Uzoh

    IPC: H01L25/16 ,  H01L33/00 ,  H01L25/10 ,  H01L27/12 ,  H01L27/15 ,  H01L25/18 ,  H01L21/321 ,  H01L21/02 ,  H01L23/00

    Abstract: Direct-bonded LED arrays and applications are provided. An example process fabricates a LED structure that includes coplanar electrical contacts for p-type and n-type semiconductors of the LED structure on a flat bonding interface surface of the LED structure. The coplanar electrical contacts of the flat bonding interface surface are direct-bonded to electrical contacts of a driver circuit for the LED structure. In a wafer-level process, micro-LED structures are fabricated on a first wafer, including coplanar electrical contacts for p-type and n-type semiconductors of the LED structures on the flat bonding interface surfaces of the wafer. At least the coplanar electrical contacts of the flat bonding interface are direct-bonded to electrical contacts of CMOS driver circuits on a second wafer. The process provides a transparent and flexible micro-LED array display, with each micro-LED structure having an illumination area approximately the size of a pixel or a smallest controllable element of an image represented on a high-resolution video display.

    Fine pitch BVA using reconstituted wafer with area array accessible for testing
    104.
    发明授权
    Fine pitch BVA using reconstituted wafer with area array accessible for testing 有权

    公开(公告)号：US10529636B2

    公开(公告)日：2020-01-07

    申请号：US15827550

    申请日：2017-11-30

    Applicant: Invensas Corporation

    Inventor： Rajesh Katkar

    IPC: H01L23/31 ,  H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L25/10 ,  H01L21/78

    Abstract: A method for simultaneously making a plurality of microelectronic packages by forming an electrically conductive redistribution structure along with a plurality of microelectronic element attachment regions on a carrier. The attachment regions being spaced apart from one another and overlying the carrier. The method also including the formation of conductive connector elements between adjacent attachment regions. Each connector element having the first or second end adjacent the carrier and the remaining end at a height of the microelectronic element. The method also includes forming an encapsulation over portions of the connector elements and subsequently singulating the assembly. into microelectronic units, each including a microelectronic element. The surface of the microelectronic unit, opposite the redistribution structure, having both the active face of the microelectronic element and the free ends of the connector elements so that both are available for connection with a component external to the microelectronic unit.

    REMOTE OPTICAL ENGINE FOR VIRTUAL REALITY OR AUGMENTED REALITY HEADSETS
    105.
    发明申请
    REMOTE OPTICAL ENGINE FOR VIRTUAL REALITY OR AUGMENTED REALITY HEADSETS 审中-公开

    公开(公告)号：US20190272802A1

    公开(公告)日：2019-09-05

    申请号：US16292705

    申请日：2019-03-05

    Applicant: Invensas Corporation

    Inventor： Belgacem Haba ,  Ilyas Mohammed ,  Rajesh Katkar

    IPC: G09G5/00 ,  G02B27/01

    Abstract: A virtual reality/augmented reality (VR/AR) headset system (including the capability for one or both of virtual reality and augmented reality) includes a remote optical engine. The remote disposition of the optical engine removes many or all of the components of the VR/AR headset system that add weight, heat, and other characteristics that can add to user discomfort in using the system from the headset. An electronic image is received and/or generated remotely at the optical engine, and is transmitted optically from the remote location to the headset to be viewed by the user. One or more optical waveguides may be used to transmit the electronic image to one or more passive displays of the headset, from the remote optical engine.

    MICROELECTRONIC PACKAGE FOR WAFER-LEVEL CHIP SCALE PACKAGING WITH FAN-OUT
    106.
    发明申请
    MICROELECTRONIC PACKAGE FOR WAFER-LEVEL CHIP SCALE PACKAGING WITH FAN-OUT 审中-公开

    公开(公告)号：US20190096861A1

    公开(公告)日：2019-03-28

    申请号：US16201569

    申请日：2018-11-27

    Applicant: Invensas Corporation

    Inventor： Rajesh Katkar ,  Ashok S. Prabhu

    IPC: H01L25/10 ,  H01L23/00 ,  H01L23/31 ,  H01L21/48 ,  H01L21/60 ,  H01L21/56

    Abstract: Apparatuses and methods relating generally to a microelectronic package for wafer-level chip scale packaging with fan-out are disclosed. In an apparatus, there is a substrate having an upper surface and a lower surface opposite the upper surface. A microelectronic device is coupled to the upper surface with the microelectronic device in a face-up orientation. Wire bond wires are coupled to and extending away from the upper surface. Posts of the microelectronic device extend away from a front face thereof. Conductive pads are formed in the substrate associated with the wire bond wires for electrical conductivity.

    Multi-chip modules formed using wafer-level processing of a reconstitute wafer
    107.
    发明授权
    Multi-chip modules formed using wafer-level processing of a reconstitute wafer 有权

    公开(公告)号：US10217720B2

    公开(公告)日：2019-02-26

    申请号：US15624494

    申请日：2017-06-15

    Applicant: Invensas Corporation

    Inventor： Liang Wang ,  Rajesh Katkar

    IPC: H01L25/10 ,  H01L25/065 ,  H01L23/31 ,  H01L25/00 ,  H01L21/56 ,  H01L21/768 ,  H01L23/00

    Abstract: Apparatuses and methods are described. This apparatus includes a bridge die having first contacts on a die surface being in a molding layer of a reconstituted wafer. The reconstituted wafer has a wafer surface including a layer surface of the molding layer and the die surface. A redistribution layer on the wafer surface includes electrically conductive and dielectric layers to provide conductive routing and conductors. The conductors extend away from the die surface and are respectively coupled to the first contacts at bottom ends thereof. At least second and third IC dies respectively having second contacts on corresponding die surfaces thereof are interconnected to the bridge die and the redistribution layer. A first portion of the second contacts are interconnected to top ends of the conductors opposite the bottom ends thereof in part for alignment of the at least second and third IC dies to the bridge die.

    Capacitors using porous alumina structures
    108.
    发明授权
    Capacitors using porous alumina structures 有权

    公开(公告)号：US10147548B2

    公开(公告)日：2018-12-04

    申请号：US14733269

    申请日：2015-06-08

    Applicant: Invensas Corporation

    Inventor： Rajesh Katkar ,  Cyprian Emeka Uzoh

    IPC: H01G4/33 ,  H01G4/08 ,  H01G4/01 ,  H01G4/10 ,  H01L49/02 ,  H01M4/80 ,  H01G4/38

    Abstract: Capacitors and methods of making the same are disclosed herein. In one embodiment, a capacitor comprises a structure having first and second oppositely facing surfaces and a plurality of pores each extending in a first direction from the first surface towards the second surface, and each having pore having insulating material extending along a wall of the pore; a first conductive portion comprising an electrically conductive material extending within at least some of the pores; and a second conductive portion comprising a region of the structure consisting essentially of aluminum surrounding individual pores of the plurality of pores, the second conductive portion electrically isolated from the first conductive portion by the insulating material extending along the walls of the pores.

    Fan-Out Wafer Level Package with Resist Vias
    109.
    发明申请
    Fan-Out Wafer Level Package with Resist Vias 审中-公开

    公开(公告)号：US20180301350A1

    公开(公告)日：2018-10-18

    申请号：US15873218

    申请日：2018-01-17

    Applicant: Invensas Corporation

    Inventor： Belgacem Haba ,  Ilyas Mohammed ,  Rajesh Katkar

    IPC: H01L21/48 ,  H01L21/56 ,  H01L21/78 ,  H01L23/538 ,  H01L23/498 ,  H01L23/00 ,  H01L25/10

    Abstract: Fan-out wafer level packages with resist vias are provided. In an implementation, an example wafer level process or panel fabrication process includes adhering a die to a carrier, applying a temporary resist layer over the die and the carrier, developing the resist layer to form channels or spaces, filling the channels or the spaces with a molding material, removing the remaining resist to create vias in the molding material, and metalizing the vias in the molding material to provide conductive vias for the microelectronics package. The methods automatically create good via and pad alignment. In another implementation, an example process includes adhering a die to a carrier, applying a permanent resist layer over the die and the carrier, developing the resist layer to form vias in the resist layer, and metalizing the vias in the remaining resist of the permanent resist layer to provide conductive vias for the microelectronics package. Assemblies may be constructed with the semiconductor dies face-up or face-down. One or more redistribution layers (RDLs) may be built on one or both sides of an assembly with resist vias.

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