Abstract:
A method for anodizing silicon substrate includes forming an n-type silicon embedded layer (21) made of n-type silicon on a predetermined area of a first surface of the p-type single crystal silicon substrate (2). N-type silicon layers (4, 6) are formed on the upper surface of the p-type single crystal silicon substrate (2) and on the n-type silicon embedded layer (21). Silicon diffusion layers (5, 7) containing high-concentration p-type impurities are formed on predetermined areas of the n-type silicon layers (4, 6) to contact the n-type silicon embedded layer (21). An electrode layer (13) is formed on the lower surface of the p-type silicon substrate (2). The anode of a DC power source (15) is connected to the electrode layer (13), and the cathode is connected to a counter electrode (23), which is opposed to the p-type silicon substrate (2). A current is intensively applied to an area corresponding to an opening (21a) of the n-type silicon layer (4) in a direction from the lower surface to the upper surface of the p-type single crystal silicon substrate (2), which makes the area porous.
Abstract:
A novel porous film is disclosed comprising a network of silicon columns in a continuous void which may be fabricated using high density plasma deposition at low temperatures, i.e., less than about 250° C. This silicon film is a two-dimensional nano-sized array of rodlike columns. This void-column morphology can be controlled with deposition conditions and the porosity can be varied up to 90%. The simultaneous use of low temperature deposition and etching in the plasma approach utilized, allows for the unique opportunity of obtaining columnar structure, a continuous void, and polycrystalline column composition at the same time. Unique devices may be fabricated using this porous continuous film by plasma deposition of this film on a glass, metal foil, insulator or plastic substrates.
Abstract:
A native oxide film is formed on the surface of a silicon substrate. The native oxide film has at least island-shaped imperfect SiO.sub.2 regions not formed with a perfect SiO.sub.2 film. Before the native oxide film is formed, a mask layer having a necessary opening is formed over the silicon substrate, according to necessity. The silicon substrate is etched in a vapor phase via the imperfect SiO.sub.2 regions of the native oxide film to form a hollow under the native oxide film at least at a partial region thereof. An upper film is formed on the native oxide film to cover and close the imperfect SiO.sub.2 regions. In this manner, a minute hollow can be formed in the silicon substrate with good controllability.
Abstract:
An ultra-high charge density electret is disclosed. The ultra-high charge density electret includes a three-dimensional structure having a plurality of sidewalls. A porous silicon dioxide film is formed on the plurality of sidewalls, and the porous silicon dioxide film is charged with a plurality of positive or negative ions.
Abstract:
A method of processing a semiconductor substrate having a first conductivity type includes, in part, forming a first implant region of a second conductivity type in the semiconductor substrate where the first implant region is characterized by a first depth, forming a second implant region of the first conductivity type in the semiconductor substrate where the second implant region is characterized by a second depth smaller than the first depth, forming a porous layer within the semiconductor substrate where the porous layer is adjacent the first implant region, and growing an epitaxial layer on the semiconductor substrate thereby causing the porous layer to collapse and form a cavity.
Abstract:
A method of producing a semiconductor device includes providing a carrier structure having a semiconductor substrate; applying or introducing a precursor substance onto or into the carrier structure, treating the precursor substance for producing a porous matrix structure; introducing a functionalization substance into the porous matrix structure.
Abstract:
A vacuum-cavity-insulated flow sensor and related fabrication method are described. The sensor comprises a porous silicon wall with numerous vacuum-pores which is created in a silicon substrate, a porous silicon membrane with numerous vacuum-pores which is surrounded and supported by the porous silicon wall, and a cavity with a vacuum-space which is disposed beneath the porous silicon membrane and surrounded by the porous silicon wall. The fabrication method includes porous silicon formation and silicon polishing in HF solution.
Abstract:
A single silicon wafer micromachined thermal conduction sensor is described. The sensor consists of a heat transfer cavity with a flat bottom and an arbitrary plane shape, which is created in a silicon substrate. A heated resistor with a temperature dependence resistance is deposed on a thin film bridge, which is the top of the cavity. A heat sink is the flat bottom of the cavity and parallel to the bridge completely. The heat transfer from the heated resistor to the heat sink is modulated by the change of the thermal conductivity of the gas or gas mixture filled in the cavity. This change can be measured to determine the composition concentration of the gas mixture or the pressure of the air in a vacuum system.
Abstract:
A single silicon wafer micromachined thermal conduction sensor is described. The sensor consists of a heat transfer cavity with a flat bottom and an arbitrary plane shape, which is created in a silicon substrate. A heated resistor with a temperature dependence resistance is deposed on a thin film bridge, which is the top of the cavity. A heat sink is the flat bottom of the cavity and parallel to the bridge completely. The heat transfer from the heated resistor to the heat sink is modulated by the change of the thermal conductivity of the gas or gas mixture filled in the cavity. This change can be measured to determine the composition concentration of the gas mixture or the pressure of the air in a vacuum system.
Abstract:
The invention provides an electronic device package and fabrication method thereof. The electronic device package includes a sensor chip. An upper surface of the sensor chip comprises a sensing film. A covering plate having an opening structure covers the upper surface of the sensor chip. A cavity is between the covering plate and the sensor chip, corresponding to a position of the sensing film, where the cavity communicates with the opening structure. A spacer is between the covering plate and the sensor chip, surrounding the cavity. A pressure releasing region is between the spacer and the sensing film.