公开(公告)号：US20240182292A1

公开(公告)日：2024-06-06

申请号：US18437345

申请日：2024-02-09

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ting-Jung Chen

IPC: B81B3/00 ,  B81C1/00 ,  G02B7/02 ,  H04N23/54 ,  H04N23/68

CPC classification number: B81B3/0072 ,  B81C1/00666 ,  H04N23/54 ,  H04N23/687 ,  B81B2203/0118 ,  B81B2203/019 ,  B81B2203/0307 ,  B81C2201/0105 ,  B81C2201/0178 ,  G02B7/021

Abstract: The present disclosure relates to an integrated chip structure. The integrated chip structure includes a MEMS (microelectromechanical systems) actuator. The MEMS actuator has an anchor. A proof mass continuously wraps around the anchor in a closed loop. One or more curved cantilevers are coupled between the proof mass and a frame. The frame wraps around the proof mass. The one or more curved cantilevers include curved outer surfaces arranged directly between a sidewall of the frame and a sidewall of the proof mass, as viewed in a top-view.

公开(公告)号：US11731164B2

公开(公告)日：2023-08-22

申请号：US17449235

申请日：2021-09-28

Applicant: The Board of Trustees of the Leland Stanford Junior University

Inventor： Bo Ma ,  Kamyar Firouzi ,  Butrus T. Khuri-Yakub ,  Jose Joseph

IPC: B06B1/02 ,  B06B1/06 ,  B81B3/00 ,  B81C1/00 ,  G01N29/06 ,  G01N29/24 ,  G01N29/22

CPC classification number: B06B1/0215 ,  B06B1/0292 ,  B06B1/0651 ,  B06B1/0662 ,  B81B3/0021 ,  B81C1/00166 ,  G01N29/0654 ,  G01N29/2406 ,  B06B2201/55 ,  B81B2201/0271 ,  B81B2203/04 ,  B81C2201/0157 ,  B81C2201/0178 ,  G01N29/22

Abstract: Aspects of this disclosure relate to driving a capacitive micromachined ultrasonic transducer (CMUT) with a pulse train of unipolar pulses. The CMUT may be electrically excited with a pulse train of unipolar pulses such that the CMUT operates in a continuous wave mode. In some embodiments, the CMUT may have a contoured electrode.

公开(公告)号：US10053360B1

公开(公告)日：2018-08-21

申请号：US15685879

申请日：2017-08-24

Applicant: Kionix, Inc.

Inventor： Martin Heller

IPC: H01L21/00 ,  B81C1/00

CPC classification number: B81C1/00047 ,  B81C1/00095 ,  B81C2201/0109 ,  B81C2201/0115 ,  B81C2201/0132 ,  B81C2201/0171 ,  B81C2201/0178

Abstract: A method of processing a semiconductor substrate having a first conductivity type includes, in part, forming a first implant region of a second conductivity type in the semiconductor substrate where the first implant region is characterized by a first depth, forming a second implant region of the first conductivity type in the semiconductor substrate where the second implant region is characterized by a second depth smaller than the first depth, forming a porous layer within the semiconductor substrate where the porous layer is adjacent the first implant region, and growing an epitaxial layer on the semiconductor substrate thereby causing the porous layer to collapse and form a cavity.

公开(公告)号：US09446947B2

公开(公告)日：2016-09-20

申请号：US14467521

申请日：2014-08-25

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Earl Vedere Atnip ,  Raul Enrique Barreto ,  Kelly J. Taylor

IPC: B81C1/00

CPC classification number: B81C1/00666 ,  B81B3/0072 ,  B81B2203/0109 ,  B81B2203/0118 ,  B81C1/00365 ,  B81C2201/0108 ,  B81C2201/0132 ,  B81C2201/0167 ,  B81C2201/0178

Abstract: A MEMS device is formed by forming a sacrificial layer over a substrate and forming a first metal layer over the sacrificial layer. Subsequently, the first metal layer is exposed to an oxidizing ambient which oxidizes a surface layer of the first metal layer where exposed to the oxidizing ambient, to form a native oxide layer of the first metal layer. A second metal layer is subsequently formed over the native oxide layer of the first metal layer. The sacrificial layer is subsequently removed, forming a released metal structure.

Abstract translation: 通过在衬底上形成牺牲层并在牺牲层上形成第一金属层来形成MEMS器件。 随后，将第一金属层暴露于氧化环境中，氧化暴露于氧化环境的第一金属层的表面层，以形成第一金属层的天然氧化物层。 随后在第一金属层的自然氧化物层上形成第二金属层。 随后去除牺牲层，形成释放的金属结构。

公开(公告)号：US20110207335A1

公开(公告)日：2011-08-25

申请号：US12709981

申请日：2010-02-22

Applicant: Tymon Barwicz

Inventor： Tymon Barwicz

IPC: H01L21/316

CPC classification number: H01L29/0665 ,  B81B2203/0109 ,  B81C1/00833 ,  B81C2201/0178 ,  B81C2201/053 ,  B82Y10/00 ,  H01L29/0673 ,  H01L29/66439 ,  H01L29/775

Abstract: Techniques for preventing bending/buckling of suspended micro/nanostructures during oxidation are provided. In one aspect, a method for oxidizing a structure is provided. The method includes providing the structure having at least one suspended element selected from the group consisting of: a microstructure, a nanostructure and a combination thereof; surrounding the at least one suspended element in a cladding material; and oxidizing the at least one suspended element through the cladding material, wherein the cladding material physically constrains and thereby prevents distortion of the at least one suspended element during the oxidation.

Abstract translation: 提供了用于在氧化期间防止悬浮的微/纳米结构的弯曲/屈曲的技术。 一方面，提供一种氧化结构的方法。 该方法包括提供具有至少一个悬浮元素的结构，所述悬浮元素选自：微结构，纳米结构及其组合; 围绕包层材料中的至少一个悬挂元件; 以及通过所述包层材料氧化所述至少一个悬浮元件，其中所述包层材料物理地约束并由此防止所述至少一个悬浮元件在氧化期间的变形。

公开(公告)号：US20060110842A1

公开(公告)日：2006-05-25

申请号：US10996234

申请日：2004-11-23

Applicant: Yuh-Hwa Chang ,  Fei-Yun Chen ,  Jiann-Tyng Tzeng ,  Cheng-Yu Chu ,  Chun-Kai Peng ,  Chih-Chieh Yeh ,  Chih-Heng Po ,  Dah-Chuen Ho

Inventor： Yuh-Hwa Chang ,  Fei-Yun Chen ,  Jiann-Tyng Tzeng ,  Cheng-Yu Chu ,  Chun-Kai Peng ,  Chih-Chieh Yeh ,  Chih-Heng Po ,  Dah-Chuen Ho

IPC: H01L21/00 ,  H01L31/0203

CPC classification number: B81C1/00253 ,  B81C2201/0178 ,  B81C2201/053

Abstract: The disclosure relates to a method and apparatus for preventing extrusion or spiking of a metal atom from a metallization layer to other layers of a silicon wafer. In one embodiment, the method includes forming a silicon-on-ship device with a MEMS component on the substrate. The MEMS component may include one or more metal or metallic alloys. To prevent spiking from the MEMS component, the sides thereof can be coated with one ore more spacer or barrier layers. In one embodiment, oxygen plasma and thermal oxidation methods are used to deposit spacers. In another embodiment, an oxide layer is deposited over the wafer, covering the substrate and the MEMS component. Selective etching or anisotropic etching can be used to remove the oxide layer from certain regions of the MEMS and the substrate while covering the sidewalls. An amorphous silicon layer can then be deposited to cover the MEMS device.

Abstract translation: 本公开涉及一种用于防止金属原子从金属化层挤出或尖峰到硅晶片其它层的方法和装置。 在一个实施例中，该方法包括在衬底上形成具有MEMS部件的在船上的硅装置。 MEMS组件可以包括一种或多种金属或金属合金。 为了防止从MEMS部件尖尖，其侧面可以涂覆一个或多个间隔物或阻挡层。 在一个实施例中，使用氧等离子体和热氧化方法来沉积间隔物。 在另一个实施例中，氧化物层沉积在晶片上，覆盖衬底和MEMS部件。 可以使用选择性蚀刻或各向异性蚀刻从覆盖侧壁的MEMS和衬底的某些区域去除氧化物层。 然后可以沉积非晶硅层以覆盖MEMS器件。

公开(公告)号：US06846746B2

公开(公告)日：2005-01-25

申请号：US10137543

申请日：2002-05-01

Applicant: Michael Rattner ,  Jeffrey D. Chinn

Inventor： Michael Rattner ,  Jeffrey D. Chinn

IPC: B81C1/00 ,  H01L21/3065 ,  H01L21/302

CPC classification number: B81C1/00611 ,  B81B2203/033 ,  B81C2201/0126 ,  B81C2201/0178 ,  H01L21/3065 ,  H01L21/30655

Abstract: Disclosed herein is a method of smoothing a trench sidewall after a deep trench silicon etch process which minimizes sidewall scalloping present after the silicon trench etch. The method comprises exposing the silicon trench sidewall to a plasma generated from a fluorine-containing gas, at a process chamber pressure within the range of about 1 mTorr to about 30 mTorr, for a time period within the range of about 10 seconds to about 600 seconds. A substrate bias voltage within the range of about −10 V to about −40 V is applied during the performance of the post-etch treatment method of the invention.

Abstract translation: 这里公开了一种在深沟槽硅蚀刻工艺之后平滑沟槽侧壁的方法，其最小化在硅沟槽蚀刻之后存在的侧壁扇形。 该方法包括将硅沟槽侧壁暴露于在约1mTorr至约30mTorr范围内的处理室压力下从含氟气体产生的等离子体，时间范围为约10秒至约600 秒。 在本发明的蚀刻后处理方法的执行期间，施加约-10V至约-40V范围内的衬底偏置电压。

公开(公告)号：US20020079490A1

公开(公告)日：2002-06-27

申请号：US09969792

申请日：2001-10-04

Applicant: Mitsubishi Denki Kabushiki Kaisha

Inventor： Shinichi Izuo ,  Hiroshi Ohji ,  Kazuhiko Tsutsumi

IPC: H01L023/58

CPC classification number: B81C1/00111 ,  B81B2201/0214 ,  B81C2201/0114 ,  B81C2201/0178 ,  G01N27/44791

Abstract: Providing a columnar structure having a uniform shape and excellent heat resistance and mechanical strength that is formed on a substrate of silicon, a method of preparing the structure, and a DNA separation device prepared by the method. A structure has, on a substrate made of silicon, columns of which main surface is covered with a thermally oxidized film. The columns are made of the thermally oxidized film only or of the thermally oxidized film and silicon. The thermally oxidized film formed on the columns is connected to those formed on the surface or inside of the substrate.

Abstract translation: 提供具有均匀形状的柱状结构，并且在硅衬底上形成的优异的耐热性和机械强度，制备该结构的方法以及通过该方法制备的DNA分离装置。 在由硅制成的基板上，在主表面被热氧化膜覆盖的列中， 柱仅由热氧化膜或热氧化膜和硅制成。 形成在列上的热氧化膜与在基板的表面或内部形成的热氧化膜连接。

公开(公告)号：US06342427B1

公开(公告)日：2002-01-29

申请号：US09473968

申请日：1999-12-29

Applicant: Chang Auck Choi ,  Chi Hoon Jun ,  Won Ick Jang ,  Yun Tae Kim

Inventor： Chang Auck Choi ,  Chi Hoon Jun ,  Won Ick Jang ,  Yun Tae Kim

IPC: H01L2100

CPC classification number: B81C1/00047 ,  B81B2203/033 ,  B81C2201/0133 ,  B81C2201/0178 ,  B81C2203/0136

Abstract: A method for forming a micro cavity is disclosed. In the method for forming the cavity, a first layer is formed on a silicon layer and a trench is formed in the silicon layer by selectively etching the silicon layer. A second and a third layers are formed on the trench and on the silicon layer. Etching holes are formed through the third layer by partially etching the third layer. A cavity is formed between the silicon layer and the third layer after the second layer is removed through the etching holes. Therefore, the cavity having a large size can be easily formed and sealed in the silicon layer by utilizing the volume expansion of the silicon or the poly silicon layer. Also, a vacuum micro cavity can be formed according as a low vacuum CVD oxide layer or a nitride layer formed on the etching holes which are partially opened after the thermal oxidation process by controlling the size of the etching holes concerning the other portion of the poly silicon layer.

Abstract translation: 公开了一种用于形成微腔的方法。 在形成空腔的方法中，在硅层上形成第一层，并且通过选择性地蚀刻硅层，在硅层中形成沟槽。 在沟槽和硅层上形成第二和第三层。 通过部分地蚀刻第三层，通过第三层形成蚀刻孔。 在通过蚀刻孔除去第二层之后，在硅层和第三层之间形成空穴。 因此，通过利用硅或多晶硅层的体积膨胀，可以容易地在硅层中形成并密封具有大尺寸的空腔。 此外，可以根据在热氧化处理后部分打开的蚀刻孔上形成的低真空CVD氧化物层或氮化物层，通过控制与聚合物的其它部分相关的蚀刻孔的尺寸，形成真空微腔 硅层。

公开(公告)号：US5736430A

公开(公告)日：1998-04-07

申请号：US480267

申请日：1995-06-07

Applicant: James D. Seefeldt ,  Michael F. Mattes

Inventor： James D. Seefeldt ,  Michael F. Mattes

IPC: G01L9/04 ,  B81B3/00 ,  G01L9/00 ,  G01P15/08 ,  G01P15/12 ,  H01L29/84 ,  H01L21/465

CPC classification number: B81C1/00158 ,  G01L9/0042 ,  G01L9/0055 ,  G01P15/0802 ,  G01P15/123 ,  B81B2203/0315 ,  B81C2201/0115 ,  B81C2201/0178 ,  Y10S438/96

Abstract: A method of forming apparatus including a force transducer on a silicon substrate having an upper surface, the silicon substrate including a dopant of one of the n-type or the p-type, the force transducer including a cavity having spaced side walls and a diaphragm supported in the cavity, the diaphragm extending between the side walls of the cavity, comprising the steps of: a. implant in the substrate a layer of a dopant of the one of the n-type or the p-type; b. deposit an epitaxial layer on the upper surface of the substrate, the epitaxial layer including a dopant of the other of the n-type or the p-type; c. implant spaced sinkers through the epitaxial layer and into electrical connection with the layer of a dopant of the one of the n-type or the p-type, each of the sinkers including a dopant of the one of the n-type or the p-type; d. anodize the substrate to form porous silicon of the sinkers and the layer; e. oxidize the porous silicon to form silicon dioxide; and f. etch the silicon dioxide to form the cavity and diaphragm.

Abstract translation: 一种形成装置的方法，包括在具有上表面的硅衬底上的力换能器，所述硅衬底包括n型或p型中的一种的掺杂剂，所述力传感器包括具有间隔开的侧壁的空腔和隔膜 支撑在空腔中，隔膜在空腔的侧壁之间延伸，包括以下步骤：a。 在衬底中注入n型或p型之一的掺杂剂层; b。 在衬底的上表面上沉积外延层，所述外延层包括n型或p型中另一种的掺杂剂; C。 通过外延层注入间隔的沉降片并与n型或p型之一的掺杂剂层电连接，每个沉降片包括n型或p型之一的掺杂剂， 类型; d。 阳极氧化基板以形成沉降片和层的多孔硅; e。 氧化多孔硅以形成二氧化硅; 和f。 蚀刻二氧化硅以形成空腔和隔膜。