公开(公告)号：US20060183332A1

公开(公告)日：2006-08-17

申请号：US11341613

申请日：2006-01-30

Applicant: Seok-jin Kang

Inventor： Seok-jin Kang

IPC: H01L21/302

CPC classification number: B81C1/0015 ,  B81C2201/019

Abstract: A method of manufacturing a floating structure capable of providing increased device yield. The method includes: a) forming an insulation film, a predetermined area of which is removed, between a first substrate and a second substrate; and b) forming a floating structure in the removed predetermined area.

Abstract translation: 制造能够提高器件产量的浮动结构的方法。 该方法包括：a）在第一基板和第二基板之间形成预定区域被除去的绝缘膜; 以及b）在去除的预定区域中形成浮动结构。

公开(公告)号：US20060166463A1

公开(公告)日：2006-07-27

申请号：US11336267

申请日：2006-01-20

Applicant: Thor Bakke ,  Martin Friedrichs ,  Benjamin Volker ,  Thomas Haase

Inventor： Thor Bakke ,  Martin Friedrichs ,  Benjamin Volker ,  Thomas Haase

IPC: H01L21/30

CPC classification number: B81C1/00142 ,  B81B2201/042 ,  B81C1/00611 ,  B81C2201/0121 ,  B81C2201/019 ,  G02B26/0833

Abstract: A method of producing a device with a movable portion spaced apart from a support wafer comprises a step of providing the support wafer having a structured surface and a further step of providing a device wafer with a backing layer and a device layer disposed thereon. Further, the method comprises the step of generating a first planarization layer from a first starting material on the support wafer with a first method to fill in the structures of the structured surface of the support wafer, whereby a surface with a first degree of planarization is obtained. Further, the method comprises a step of generating a second planarization layer from a second starting material on the planarized surface of the support wafer with a second method to obtain a surface with a second degree of planarization, which is higher than the first degree of planarization, wherein the first and second planarization layers can be removed together. Additionally, the support wafer is connected to the device wafer such that the device layer and the planarized surface of the support wafer are connected. Then, removing the backing layer of the device wafer is performed, followed by structuring the resulting structure and removing the first and second planarization layers via a common method to generate the moveable portion of the device.

Abstract translation: 制造具有与支撑晶片间隔开的可移动部分的装置的方法包括提供具有结构化表面的支撑晶片的步骤，以及提供具有背衬层和设置在其上的器件层的器件晶片的另外步骤。 此外，该方法包括以第一种填充支撑晶片的结构化表面的结构的方式从支撑晶片上的第一起始材料产生第一平坦化层的步骤，由此具有第一程度的平坦化的表面是 获得。 此外，该方法包括以第二种方法从支撑晶片的平坦化表面上的第二起始材料产生第二平坦化层的步骤，以获得具有比第一平坦化程度高的第二平坦度的表面 ，其中第一和第二平坦化层可以一起去除。 此外，支撑晶片连接到器件晶片，使得器件层和支撑晶片的平坦化表面被连接。 然后，去除器件晶片的背衬层，然后构造所得到的结构，并且通过常用的方法去除第一和第二平坦化层以产生器件的可移动部分。

公开(公告)号：US20060093787A1

公开(公告)日：2006-05-04

申请号：US10977141

申请日：2004-10-29

Applicant: Chien-Hua Chen ,  Barry Snyder ,  Ronald Hellekson

Inventor： Chien-Hua Chen ,  Barry Snyder ,  Ronald Hellekson

IPC: B32B3/10

CPC classification number: B41J2/1642 ,  B41J2/16 ,  B41J2/1603 ,  B41J2/1623 ,  B41J2/1628 ,  B41J2/1629 ,  B41J2/1632 ,  B41J2/1634 ,  B81C3/001 ,  B81C2201/019 ,  H01L21/2007 ,  H01L21/76251 ,  H01L24/26 ,  H01L24/83 ,  H01L2224/8385 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01067 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1461 ,  Y10T428/24322 ,  Y10T428/24612 ,  H01L2924/00

Abstract: An electronic device comprises a substrate comprising a first surface and a second surface, a substrate carrier comprising a first surface and a second surface, and an inorganic material bonding the second surface of the substrate and the second surface of the substrate carrier.

公开(公告)号：US20050239272A1

公开(公告)日：2005-10-27

申请号：US10920043

申请日：2004-08-16

Applicant: Eike Ruttkowski ,  Gurkan Ilicali ,  Richard Luyken ,  Franz Hofmann ,  Manuela Bueno

Inventor： Eike Ruttkowski ,  Gurkan Ilicali ,  Richard Luyken ,  Franz Hofmann ,  Manuela Bueno

IPC: B81C1/00 ,  H01L21/768 ,  H01L21/44

CPC classification number: H01L21/76838 ,  B81C1/00357 ,  B81C2201/019

Abstract: Process for producing a multilayer arrangement having a metal layer, in which a metal layer is applied to a surface of a first wafer and at least one interlayer is applied to the metal layer. Furthermore, a second wafer is applied to the interlayer and then the first wafer is removed, so that the metal layer is uncovered.

Abstract translation: 制造具有金属层的多层布置方法，其中将金属层施加到第一晶片和至少一层间的表面上施加金属层。 此外，将第二晶片施加到中间层，然后移除第一晶片，使得金属层未被覆盖。

公开(公告)号：US06955975B2

公开(公告)日：2005-10-18

申请号：US10433525

申请日：2002-09-05

Applicant: Frank Reichenbach ,  Frank Fischer ,  Ralf Hausner ,  Frieder Haag ,  Eckhard Graf ,  Markus Lutz

Inventor： Frank Reichenbach ,  Frank Fischer ,  Ralf Hausner ,  Frieder Haag ,  Eckhard Graf ,  Markus Lutz

IPC: B29C65/16 ,  B29C65/60 ,  B81C1/00 ,  H01L21/20 ,  H01L21/58 ,  H01L21/60 ,  H01L21/762 ,  H01L21/30 ,  H01L21/46

CPC classification number: B29C65/1635 ,  B29C65/1612 ,  B29C65/1683 ,  B29C65/608 ,  B29C66/1122 ,  B29C66/12421 ,  B29C66/472 ,  B29C66/53461 ,  B29C66/71 ,  B29C66/712 ,  B29C66/7392 ,  B29K2083/00 ,  B29L2031/756 ,  B81C1/00269 ,  B81C1/00357 ,  B81C2201/019 ,  B81C2203/019 ,  H01L21/2007 ,  H01L21/76251 ,  H01L24/83 ,  H01L2224/80224 ,  H01L2224/80365 ,  H01L2224/80379 ,  H01L2224/804 ,  H01L2224/80488 ,  H01L2224/83224 ,  H01L2224/834 ,  H01L2224/83424 ,  H01L2224/83447 ,  H01L2224/83466 ,  H01L2224/83471 ,  H01L2224/83487 ,  H01L2224/8349 ,  H01L2224/83801 ,  H01L2924/01029 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/01014 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A method for joining a silicon plate to a second plate, a laser beam being directed through the silicon plate at the second plate. In the process, the wavelength of the laser beam is selected in such a way that only a negligibly small amount of energy is absorbed in the silicon plate. A strongly absorbent material is hotmelted by the laser beam's energy and then produces a bond between the silicon plate and the second plate.

Abstract translation: 一种用于将硅板接合到第二板的方法，激光束被引导通过硅板在第二板。 在该过程中，激光束的波长以这样一种方式选择，即在硅板中仅吸收可忽略的少量能量。 强吸收性材料被激光束的能量热熔化，然后在硅板和第二板之间产生粘结。

公开(公告)号：US20050204939A1

公开(公告)日：2005-09-22

申请号：US10516161

申请日：2003-06-02

Applicant: Jan Krejci

Inventor： Jan Krejci

IPC: G01N27/07 ,  B01D61/18 ,  B01D61/28 ,  B01D63/08 ,  B01L3/00 ,  B81B1/00 ,  B81C1/00 ,  F04B43/04 ,  G01F1/684 ,  G01N27/30 ,  G01N27/327 ,  G01N27/403 ,  G01N27/447

CPC classification number: B81C1/0046 ,  B01D61/18 ,  B01D61/28 ,  B01D63/081 ,  B01D63/088 ,  B01L3/502707 ,  B01L2300/0645 ,  B01L2300/0681 ,  B01L2300/0816 ,  B01L2300/0874 ,  B01L2300/0887 ,  B01L2400/0418 ,  B01L2400/0421 ,  B81B2201/0264 ,  B81B2203/0127 ,  B81C2201/019 ,  F04B43/043 ,  G01F1/6845 ,  G01N27/4473 ,  G01N27/44791

Abstract: Object of the present invention are components with three dimensional structure prepared by thick film technology by print, where between the printed layers is inserted at least one membrane. The membrane is according to the present to invention at least in a part of the final product. The membrane can be provided with holes which are necessary for next technological steps. The inserted membranes can have pores of the size of 50˜tm to 10 nm and a thickness of 1 to 200˜tm. Method of producing of components with three-dimensional structure by thick film printing technology according to the invention lies in that between some of the printed layers is inserted a suitable membrane, which allows to lay on next layers without influence to previous layers. The printing can be done by screen-printing.

Abstract translation: 本发明的目的是通过印刷通过厚膜技术制备的具有三维结构的部件，其中在印刷层之间插入至少一个膜。 至少在最终产品的一部分中，膜根据本发明。 膜可以设置有下一个工艺步骤所需的孔。 插入的膜可以具有50〜tm〜10nm的孔，厚度为1〜200〜tm。 通过根据本发明的厚膜印刷技术制造具有三维结构的部件的方法在于，在一些印刷层之间插入合适的膜，其允许铺设在下一层上而不影响先前的层。 打印可以通过丝网印刷完成。

公开(公告)号：US06930368B2

公开(公告)日：2005-08-16

申请号：US10630769

申请日：2003-07-31

Applicant: Peter G. Hartwell ,  Storrs T. Hoen ,  David Horsley ,  Chung Ching Yang ,  Paul P. Merchant ,  Carl P. Taussig

Inventor： Peter G. Hartwell ,  Storrs T. Hoen ,  David Horsley ,  Chung Ching Yang ,  Paul P. Merchant ,  Carl P. Taussig

IPC: G01P15/125 ,  B81B3/00 ,  B81B5/00 ,  B81B7/00 ,  B81B7/02 ,  H01L29/82 ,  H01L33/00

CPC classification number: B81B7/0041 ,  B81B2201/0235 ,  B81C2201/019 ,  B81C2203/019 ,  G01P2015/082

Abstract: A microelectromechanical system includes a first wafer, a second wafer including a moveable portion, and a third wafer. The movable portion is movable between the first wafer and the third wafer. The first wafer, the second wafer, and the third wafer are bonded together.

公开(公告)号：US20050170656A1

公开(公告)日：2005-08-04

申请号：US10771135

申请日：2004-02-02

Applicant: Steven Nasiri ,  Anthony Flannery

Inventor： Steven Nasiri ,  Anthony Flannery

IPC: B81B7/02 ,  H01L21/311

CPC classification number: B81C1/00238 ,  B81B2201/0235 ,  B81C2201/019 ,  B81C2203/0118 ,  H01L2224/29011

Abstract: A wafer-scale fabrication method for providing MEMS assemblies having a MEMS subassembly sandwiched between and bonded to a cap and a base is provided. The MEMS subassembly includes at least one MEMS device element flexibly connected to the MEMS assembly. The vertical separation between the MEMS device element and an electrode on the base is lithographically defined. Precise control of this critical vertical gap dimension is thereby provided. Fabrication cost is greatly reduced by wafer scale integration.

Abstract translation: 提供了一种用于提供MEMS组件的晶片级制造方法，所述MEMS组件具有夹在盖子和底座之间并结合到盖子和底座的MEMS子组件。 MEMS子组件包括至少一个柔性地连接到MEMS组件的MEMS器件元件。 MEMS器件元件与基底上的电极之间的垂直间隔是光刻的。 由此提供了该临界垂直间隙尺寸的精确控制。 晶圆规模集成大大降低了制造成本。

公开(公告)号：US20050164118A1

公开(公告)日：2005-07-28

申请号：US10503161

申请日：2003-01-31

Applicant: Claus Barholm -Hansen ,  Jacques Jonsmann

Inventor： Claus Barholm -Hansen ,  Jacques Jonsmann

IPC: B01J19/00 ,  B01L3/00 ,  B81C1/00 ,  G03F7/00 ,  G03F7/038 ,  G03F7/40 ,  G03C1/76

CPC classification number: B81C3/001 ,  B01J19/0093 ,  B01J2219/00783 ,  B01J2219/00833 ,  B01L3/5027 ,  B81B2201/058 ,  B81B2203/0338 ,  B81C1/00357 ,  B81C2201/019 ,  G03F7/0012 ,  G03F7/0385 ,  G03F7/40

Abstract: A method of joining a workpiece and a microstructure by light exposure, a microstructure obtainable by the method comprising a workpiece joined thereto, means thereto and use thereof; in particular a microstructure-forming composition comprising a light-sensitive, structure-forming material comprising one or more photo resist materials which are sensitive to preferably UV-light, and a light-absorbing material comprising one or more light-absorbing substances absorbing preferably IR light and being in an amount sufficient to produce heat upon exposure to said absorbed light; a microstructure-forming preparation comprising such composition; a method of producing a microstructure on a substrate; and a microstructure obtainable by the method; a method of joining a workpiece and a microstructure, a microstructure obtainable by the method comprising a workpiece joined thereto, e.g. for producing closed micro flow channels in a micro flow system; and use of such a microstructure, e.g. in lab-on-chip applications, in point-of-care systems, in high-through-put screening systems, preferably in systems for screening active compounds in fluids, in particular biological fluids.

Abstract translation: 通过曝光接合工件和微结构的方法，通过包括与其接合的工件的方法可获得的微观结构及其用途; 特别是一种微结构形成组合物，其包含光敏的结构形成材料，其包含对优选紫外光敏感的一种或多种光致抗蚀剂材料，以及光吸收材料，其包含一种或多种吸收物质优选吸收IR 并且其量足以在暴露于所述吸收的光时产生热量; 包含这种组合物的微结构形成制剂; 在基板上制造微观结构的方法; 和通过该方法获得的微结构; 接合工件和微结构的方法，通过包括与其连接的工件的方法获得的微结构，例如。 用于在微流量系统中产生闭合的微流通道; 并使用这种微结构，例如。 在片上应用中，在点到点系统中，在高通量筛选系统中，优选用于筛选流体中特别是生物流体中的活性化合物的系统。

公开(公告)号：US06875671B2

公开(公告)日：2005-04-05

申请号：US10717219

申请日：2003-11-19

Applicant: Sadeg M. Faris

Inventor： Sadeg M. Faris

IPC: B81C1/00 ,  G01R31/01 ,  H01L21/66 ,  H01L21/30

CPC classification number: B81C1/00238 ,  B81C1/0038 ,  B81C2201/019 ,  G01R31/01 ,  H01L22/20 ,  H01L23/552 ,  H01L2924/0002 ,  H01L2924/014 ,  Y10S438/977 ,  H01L2924/00

Abstract: A method for fabricating a vertical integrated circuit is disclosed. Integrated circuits are fabricated on a substrate with layers of predetermined weak and strong bond regions where deconstructed layers of integrated circuits are fabricated at or on the weak bond regions. The layers are then peeled and subsequently bonded to produce a vertical integrated circuit. An arbitrary number of layers can be bonded and stacked in to a separate vertical integrated circuit. Also disclosed are methods of creating edge interconnects and vias through the substrate to form interconnections between layers and devices thereon.