公开(公告)号：US20050205994A1

公开(公告)日：2005-09-22

申请号：US11047555

申请日：2005-02-02

Applicant: Sheng-Yuan Lee

Inventor： Sheng-Yuan Lee

IPC: H01L23/48 ,  H01L23/498 ,  H01L23/66 ,  H05K1/02 ,  H05K1/11 ,  H05K3/42

CPC classification number: H01L23/66 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2223/6616 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/3011 ,  H05K1/0251 ,  H05K1/114 ,  H05K1/116 ,  H05K3/429 ,  H05K2201/0792 ,  H05K2201/09309 ,  H05K2201/09718 ,  H01L2924/00

Abstract: A signal transmitting device with vias and solder balls comprises: at least one main structure(s), a second substrate, a third substrate, at least one via(s), at least one conductive layer(s), at least one solder pad(s) and at least one solder ball(s). The main structure comprises at least one first substrate having a first surface and a second surface, wherein the first surface has a first circuit layer disposed thereon and the second surface has a second circuit layer disposed thereon. The second substrate is disposed on the first circuit layer and the third substrate is disposed on the second circuit layer. The via passes through the second substrate, the main structure and the third substrate sequentially. The conductive layer is disposed on the rim of the via and also the second substrate and the third substrate so that a parameter representing the width of covered area on the second substrate and the third substrate is properly equal to d. The solder pad is disposed on the second substrate and is connected to the conductive layer and, the solder ball is disposed on the solder pad. An aperture corresponding to the via is formed on the first circuit layer and the second circuit layer, and a slot is arranged corresponding to the solder ball.

Abstract translation: 具有通孔和焊球的信号传输装置包括：至少一个主要结构，第二基板，第三基板，至少一个通孔，至少一个导电层，至少一个焊盘 （s）和至少一个焊球。 所述主结构包括至少一个具有第一表面和第二表面的第一基底，其中所述第一表面具有设置在其上的第一电路层，所述第二表面具有设置在其上的第二电路层。 第二基板设置在第一电路层上，第三基板设置在第二电路层上。 通孔依次通过第二基板，主结构和第三基板。 导电层设置在通孔的边缘，以及第二基板和第三基板上，使得表示第二基板和第三基板上的被覆盖区域的宽度的参数适当地等于d。 焊盘设置在第二基板上并连接到导电层，焊球设置在焊盘上。 在第一电路层和第二电路层上形成对应于通孔的孔，并且对应于焊球设置槽。

公开(公告)号：US20050202725A1

公开(公告)日：2005-09-15

申请号：US11068136

申请日：2005-02-28

Applicant: David Johnson ,  Eric Kline

Inventor： David Johnson ,  Eric Kline

IPC: H01L23/64 ,  H01R12/57 ,  H01R13/24 ,  H01R13/646 ,  H01R13/6464 ,  H01R13/6471 ,  H01R13/6473 ,  H01R13/66 ,  H01R13/719 ,  H01R33/76 ,  H01R33/945 ,  H05K1/02 ,  H05K7/10

CPC classification number: H01R13/2464 ,  H01L23/64 ,  H01L23/642 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01R12/57 ,  H01R13/2407 ,  H01R13/6464 ,  H01R13/6471 ,  H01R13/6473 ,  H01R13/6608 ,  H01R13/719 ,  H05K1/023 ,  H05K1/0231 ,  H05K1/025 ,  H05K7/1092 ,  H05K2201/0792 ,  H05K2201/10325 ,  H05K2201/10515 ,  H05K2201/1053 ,  H05K2201/10636 ,  H05K2201/10689 ,  Y02P70/611 ,  H01L2924/00

Abstract: An apparatus for providing a controlled impedance directly to predetermined contact elements within a socket, thereby reducing the “distorting” nature of the electrical interconnection system. In an illustrative embodiment of the present invention, predetermined contacts of a socket may have a resistance, inductance, capacitance, or a combination thereof incorporated therein. In another illustrative embodiment, at least one active element(s) may also be incorporated into predefined contacts. In this manner, predefined contacts may “process” the corresponding signal in a predetermined manner, defined by the circuitry incorporated on the contact itself. Illustrative functions that may be performed include, but are not limited to, amplifying, analog-to-digital converting, digital-to-analog converting, predefined logic functions, or any other function that may be performed via a combination of active and/or passive elements including a microprocessor function.

Abstract translation: 一种用于将受控阻抗直接提供给插座内的预定接触元件的设备，由此降低了电互连系统的“变形”性质。 在本发明的说明性实施例中，插座的预定触点可以具有并入其中的电阻，电感，电容或其组合。 在另一说明性实施例中，至少一个有源元件也可以并入预定义的触点中。 以这种方式，预定义的触点可以以预定的方式“处理”对应的信号，由接合体本身所包含的电路定义。 可以执行的说明性功能包括但不限于放大模数转换，数模转换，预定义逻辑功能或可以通过有源和/或数字转换的组合来执行的任何其他功能， 无源元件包括微处理器功能。

公开(公告)号：US20050116013A1

公开(公告)日：2005-06-02

申请号：US10722432

申请日：2003-11-28

Applicant: Young Kwark ,  Christian Schuster

Inventor： Young Kwark ,  Christian Schuster

IPC: H01L23/66 ,  H05K1/02 ,  B23K31/02

CPC classification number: H01L24/46 ,  H01L23/66 ,  H01L24/43 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/50 ,  H01L24/73 ,  H01L2223/6611 ,  H01L2223/6627 ,  H01L2224/43 ,  H01L2224/45014 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48465 ,  H01L2224/48599 ,  H01L2224/48699 ,  H01L2224/49174 ,  H01L2224/8502 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/1903 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/30111 ,  H05K1/0219 ,  H05K1/0243 ,  H05K2201/0792 ,  H05K2201/09236 ,  H05K2201/1028 ,  H05K2203/049 ,  H01L2924/00 ,  H01L2224/85399 ,  H01L2224/05599

Abstract: A method (and structure) of making an electronic interconnection, includes, for a signal line to be interconnected, using a plurality of bonding wires configured to provide a controlled impedance effect.

Abstract translation: 制造电子互连的方法（和结构）包括用于要互连的信号线，使用被配置为提供受控阻抗效应的多个接合线。

公开(公告)号：US20050062587A1

公开(公告)日：2005-03-24

申请号：US10668999

申请日：2003-09-24

Applicant: Wei-Chun Yang ,  Chien Chang

Inventor： Wei-Chun Yang ,  Chien Chang

IPC: H01C1/14 ,  H01C7/00 ,  H01C17/28 ,  H05K1/02 ,  H05K1/09 ,  H05K1/11 ,  H05K1/16 ,  H05K3/40 ,  H05K3/46 ,  H01C1/012

CPC classification number: H01C17/281 ,  H01C1/14 ,  H01C7/005 ,  H05K1/023 ,  H05K1/0246 ,  H05K1/095 ,  H05K1/113 ,  H05K1/167 ,  H05K3/4069 ,  H05K3/4652 ,  H05K2201/0792 ,  H05K2201/10378

Abstract: A structure and a method of a substrate with built-in via hole resistors are disclosed. The substrate structure includes a core layer made of insulating material and a plurality of via holes for filling with polymer thick film resistor. After the via holes are filled with PTFR, a solder ball or a pad is formed on both ends of the via hole to provide electrical conductivity.

Abstract translation: 公开了一种具有内置通孔电阻器的衬底的结构和方法。 基板结构包括由绝缘材料制成的芯层和用于填充聚合物厚膜电阻器的多个通孔。 在通孔填充PTFR之后，在通孔的两端形成焊球或焊盘以提供导电性。

公开(公告)号：US20040016569A1

公开(公告)日：2004-01-29

申请号：US10205725

申请日：2002-07-26

Inventor： Jason A. Mix ,  Yun Ling ,  Alok Tripathi ,  Kent E. Mallory

IPC: H05K001/11

CPC classification number: H05K1/117 ,  H01R12/721 ,  H05K1/0298 ,  H05K2201/0792 ,  H05K2201/093 ,  H05K2201/09309

Abstract: A technique to simultaneously reduce high-frequency insertion loss and cross-talk for a multi-layered add-in card is disclosed. The technique is based on selective removal of ground and power planes beneath the edge fingers. This selective removal of power and ground planes removes excess capacitance at the edge fingers, lowering the insertion loss at high frequencies, while maintaining an impedance match with an associated connector. Simultaneously, the leftover metallic ground/power plane provides electromagnetic shielding and thus reduces the cross-talk between the differential pairs. Optimum performance of the connector with minimized insertion loss and cross-talk can be obtained for high-speed analog and digital applications.

Abstract translation: 公开了同时降低多层附加卡的高频插入损耗和串扰的技术。 该技术基于选择性地去除边缘手指下方的地面和电源平面。 电源和接地层的这种选择性去除消除了边缘手指处的过剩电容，降低了高频下的插入损耗，同时保持与相关连接器的阻抗匹配。 同时，剩余的金属接地/电源平面提供电磁屏蔽，从而减少差分对之间的串扰。 对于高速模拟和数字应用，可以获得具有最小插入损耗和串扰的连接器的最佳性能。

公开(公告)号：US06641407B2

公开(公告)日：2003-11-04

申请号：US09955302

申请日：2001-09-19

Applicant: Yoshinori Murakami

Inventor： Yoshinori Murakami

IPC: H01R1200

CPC classification number: H05K3/368 ,  H01L2224/48091 ,  H01L2224/49111 ,  H01L2924/13091 ,  H01R12/52 ,  H05K1/0216 ,  H05K1/145 ,  H05K1/148 ,  H05K1/162 ,  H05K3/36 ,  H05K2201/0792 ,  H05K2201/09672 ,  H05K2201/1028 ,  H05K2201/10818 ,  H05K2201/10893 ,  H01L2924/00014 ,  H01L2924/00

Abstract: An interconnect structure has a plurality of planar interconnects (1, 2) mutually superposed with a prescribed distance therebetween and serving as interconnects between two circuit boards (A, B), each of the planar interconnects (1, 2) having at least two connection terminals (1A, 1B, 2A, 2B) at the circuit boards (1, 2). Rather than using rigid wire interconnects as done in the past to make interconnections, planar interconnects having relatively large surface areas are used to increase the line-to-line capacitance, thereby enhancing the filtering function that reduces high-frequency noise.

Abstract translation: 互连结构具有多个平面互连（1,2），它们之间以规定距离相互重叠并且用作两个电路板（A，B）之间的互连，每个平面互连（1,2）具有至少两个连接 电路板（1,2）上的端子（1A，1B，2A，2B）。 不像以前那样使用刚性的电线互连来做互连，而是使用具有相对大的表面积的平面互连来增加线对线电容，从而增强降低高频噪声的滤波功能。

公开(公告)号：US20030107056A1

公开(公告)日：2003-06-12

申请号：US10013326

申请日：2001-12-08

Applicant: NATIONAL SEMICONDUCTOR CORPORATION

Inventor： Tsun-Kit Chin ,  William Landucci

IPC: H01L027/10

CPC classification number: H05K1/025 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/642 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/0216 ,  H05K1/0298 ,  H05K1/111 ,  H05K1/162 ,  H05K2201/0792 ,  H05K2201/093 ,  H05K2201/0969 ,  H05K2201/09781 ,  H01L2924/00

Abstract: To significantly reduce parasitic capacitance of component's landing pad, the present invention forms patterned holes in reference potential layers below the pad, thus effectively increasing the dielectric distance between the pad and the reference potential planes below the pad, raising the characteristic impedance of the pad above that of the trace connected to the pad. A controlled amount of parasitic capacitance is re-introduced to the pad by forming at least one grounded metal plate adjacent to the pad, bringing the characteristic impedance of the pad to substantially match that of the trace. The distance of the metal plates from the pad, and the configuration of the patterned holes are predetermined to substantially match the pad's impedance with that of the trace.

Abstract translation: 为了显着降低部件的着陆焊盘的寄生电容，本发明在焊盘下方的参考电位层中形成图案化的孔，从而有效地增加焊盘与焊盘之下的参考电位面之间的介电距离，从而提高焊盘上方的特性阻抗 痕迹连接到垫。 通过形成与焊盘相邻的至少一个接地金属板，将受控量的寄生电容重新引入焊盘，使焊盘的特性阻抗基本上与迹线的阻抗一致。 金属板与焊盘的距离以及图案化孔的构型被预先确定，以使焊盘的阻抗与迹线的阻抗基本匹配。

公开(公告)号：US06472613B1

公开(公告)日：2002-10-29

申请号：US09677097

申请日：2000-09-29

Applicant: Jeffrey A. Reichard

Inventor： Jeffrey A. Reichard

IPC: H05K1204

CPC classification number: H05K1/144 ,  H05K1/0263 ,  H05K3/325 ,  H05K3/368 ,  H05K2201/0792 ,  H05K2201/0979 ,  H05K2201/10166 ,  H05K2201/10409

Abstract: A low-inductance connection between a first component and a second component on a first surface of a first printed-circuit board includes a second conducting path in electrical communication with a first conducting path that connects the first and second components. The second conducting path is disposed on a surface separated from the first surface of the first printed-circuit board and separated from the first printed-circuit board by an insulating layer. An electrical connector extends between the first conducting path and the second conducting path and provides electrical communication between them. The first and second conducting paths thus cooperate to provide an electrical connection having a parasitic inductance that is smaller than the parasitic inductance of the first conducting path.

Abstract translation: 在第一印刷电路板的第一表面上的第一部件和第二部件之间的低电感连接包括与连接第一和第二部件的第一导电路径电连通的第二导电路径。 第二导电路径设置在与第一印刷电路板的第一表面分离的表面上，并且通过绝缘层与第一印刷电路板分离。 电连接器在第一导电路径和第二导电路径之间延伸并且在它们之间提供电连通。 因此，第一和第二导电路径协作以提供具有小于第一导电路径的寄生电感的寄生电感的电连接。

公开(公告)号：US20020153605A1

公开(公告)日：2002-10-24

申请号：US10127082

申请日：2002-04-19

Inventor： Nai-Shung Chang

IPC: H01L023/52

CPC classification number: H01L23/49838 ,  H01L23/3128 ,  H01L23/50 ,  H01L23/5383 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2223/6611 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48233 ,  H01L2224/48237 ,  H01L2224/49111 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/30107 ,  H05K1/0216 ,  H05K1/181 ,  H05K2201/0792 ,  H05K2201/094 ,  H05K2201/10522 ,  H05K2201/10689 ,  H05K2203/049 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: A ball grid array packaging structure for sealing a silicon chip on a substrate is disclosed. The substrate includes a front wiring layer and a back wiring layer. The front wiring layer includes a plurality of inner power rings and an outer power ring. The inner power rings are attached and together they surround a central region where the silicon chip is attached. The inner power rings and the outer power ring have a substantially identical width and the outer power ring surrounds all the inner power rings. The back wiring layer has a large number of interface power balls and core power balls. The interface power balls may be further subdivided into groups of inner power balls, while each group of inner power balls corresponds and couples with one of the inner power rings of the front wiring layer. The core power balls connect with the outer power ring and surround the interface power balls.

Abstract translation: 公开了一种用于密封衬底上的硅芯片的球栅阵列封装结构。 基板包括前布线层和背布线层。 前布线层包括多个内功率环和外电源环。 内部功率环被连接在一起，它们围绕硅芯片附接的中心区域。 内部动力环和外部动力环具有基本上相同的宽度，并且外部动力环围绕所有内部动力环。 背面布线层具有大量的接口电源球和核心电源球。 接口动力球可以进一步细分为内部动力球组，而每组内部动力球对应于前部线路层的内部动力环中的一个。 核心电源球与外部电源环连接，并围绕接口电源球。

公开(公告)号：US20020037656A1

公开(公告)日：2002-03-28

申请号：US09955302

申请日：2001-09-19

Inventor： Yoshinori Murakami

IPC: H05K001/00

CPC classification number: H05K3/368 ,  H01L2224/48091 ,  H01L2224/49111 ,  H01L2924/13091 ,  H01R12/52 ,  H05K1/0216 ,  H05K1/145 ,  H05K1/148 ,  H05K1/162 ,  H05K3/36 ,  H05K2201/0792 ,  H05K2201/09672 ,  H05K2201/1028 ,  H05K2201/10818 ,  H05K2201/10893 ,  H01L2924/00014 ,  H01L2924/00

Abstract: An interconnect structure has a plurality of planar interconnects (1, 2) mutually superposed with a prescribed distance therebetween and serving as interconnects between two circuit boards (A, B), each of the planar interconnects (1, 2) having at least two connection terminals (1A, 1B, 2A, 2B) at the circuit boards (1, 2). Rather than using rigid wire interconnects as done in the past to make interconnections, planar interconnects having relatively large surface areas are used to increase the line-to-line capacitance, thereby enhancing the filtering function that reduces high-frequency noise.

Abstract translation: 互连结构具有多个平面互连（1,2），它们之间以规定距离相互重叠并且用作两个电路板（A，B）之间的互连，每个平面互连（1,2）具有至少两个连接 电路板（1,2）上的端子（1A，1B，2A，2B）。 不像以前那样使用刚性的电线互连来做互连，而是使用具有相对大的表面积的平面互连来增加线对线电容，从而增强降低高频噪声的滤波功能。