公开(公告)号：US4328614A

公开(公告)日：1982-05-11

申请号：US133255

申请日：1980-03-24

Applicant: Robert L. Schelhorn

Inventor： Robert L. Schelhorn

IPC: H05K1/05 ,  H05K3/40 ,  H05K3/44 ,  H05K3/04

CPC classification number: H05K3/445 ,  H05K1/053 ,  H05K2201/09636 ,  H05K2201/09881 ,  H05K2201/10416 ,  H05K3/4046 ,  Y10T29/49147

Abstract: In accordance with this invention a procelain coated metal board is provided which has flat surfaces and further has electrical connections between the face and reverse surfaces of the board. In accordance with a further aspect of this invention the boards of this invention are obtained by a method in which the connecting pins are sealed in a spaced relationship in apertures in the metal core of the board and insulated from the core prior to the application of the procelain to the surfaces of the core.

Abstract translation: 根据本发明，提供了一种具有平坦表面并且还具有电路板的表面和反面之间的电连接的镀层金属板。 根据本发明的另一方面，本发明的板是通过一种方法获得的，其中连接销在板的金属芯中的孔中以间隔的关系密封，并在施加之前与芯绝缘 原子核到核心的表面。

公开(公告)号：US11792916B2

公开(公告)日：2023-10-17

申请号：US17567332

申请日：2022-01-03

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Jae Han Park ,  Woo Seok Yang

IPC: H05K1/02 ,  H05K3/10 ,  H05K1/11

CPC classification number: H05K1/0224 ,  H05K1/116 ,  H05K3/107 ,  H05K2201/09036 ,  H05K2201/09636

Abstract: A printed circuit board includes an insulating layer; a recess portion disposed on one surface of the insulating layer; and a circuit layer disposed on the one surface of the insulating layer and including a signal pattern and a ground pattern. At least a portion of the ground pattern covers at least a portion of the recess portion.

公开(公告)号：US20230319997A1

公开(公告)日：2023-10-05

申请号：US17710944

申请日：2022-03-31

Applicant: Intel Corporation

Inventor： Aslam HASWAREY ,  Anne AUGUSTINE ,  Yan Fen SHEN

IPC: H05K1/16 ,  H05K3/42 ,  H05K3/00

CPC classification number: H05K1/162 ,  H05K3/429 ,  H05K3/0094 ,  H05K2201/09636 ,  H05K2201/0959 ,  H05K2201/09563 ,  H05K1/181

Abstract: Embodiments herein relate to systems, apparatuses, or processes to using vias, or plated through holes (PTH), within a substrate or within a sub laminate to create capacitors. The interior of a via may have a first layer, or coating, of an electrically conductive material such as copper, formed on the sides of the via. A second layer including a dielectric material is placed on the first layer of the electrically conductive material. A third layer of electrically conductive material may then be placed on the second layer of the dielectric material. Other embodiments may be described and/or claimed.

公开(公告)号：US11758644B2

公开(公告)日：2023-09-12

申请号：US17319577

申请日：2021-05-13

Applicant: Dell Products L.P.

Inventor： Jason Pritchard ,  Charles W. Ziegler, IV ,  Qianwen Wang ,  Lingyu Kong

IPC: H05K1/02 ,  H05K1/11

CPC classification number: H05K1/0222 ,  H05K2201/09618 ,  H05K2201/09636

Abstract: A circuit board may include a traditional via electrically coupled to a first layer of the circuit board and coupled to a second layer of the circuit board and a slotted via formed within the circuit board proximate to the traditional via, the slotted via comprising an opening through a first surface and a second surface of the circuit board and a layer of conductive material formed on interior walls of the opening.

公开(公告)号：US11751323B2

公开(公告)日：2023-09-05

申请号：US17443742

申请日：2021-07-27

Applicant: DELL PRODUCTS, LP

Inventor： Sandor Farkas ,  Bhyrav Mutnury

IPC: H05K1/02 ,  H05K1/18 ,  H05K1/11 ,  H05K3/46

CPC classification number: H05K1/0245 ,  H05K1/115 ,  H05K3/4644 ,  H05K1/18 ,  H05K2201/09636 ,  H05K2201/09672

Abstract: A printed circuit board (PCB) is provided for transmitting a differential signal. The PCB includes first and second conductive signal layers. The first conductive signal layer includes a first positive trace of the differential signal and a first negative trace of the differential signal. The second conductive signal layer includes a second positive trace of the differential signal and a second negative trace of the differential signal. The first positive trace is adjacent to the first negative trace, and the second positive trace is adjacent to the second negative trace and directly below the first negative trace.

公开(公告)号：US20190208618A1

公开(公告)日：2019-07-04

申请号：US16234829

申请日：2018-12-28

Applicant: CELESTICA TECHNOLOGY CONSULTANCY (SHANGHAI) CO. LTD

Inventor： JIWEI WEN ,  CHENXIA FENG ,  LIANG CHEN ,  LIJUAN QU

IPC: H05K1/02 ,  H05K1/11 ,  H05K3/00 ,  H05K3/04

CPC classification number: H05K1/0216 ,  H05K1/115 ,  H05K3/0047 ,  H05K3/043 ,  H05K2201/09227 ,  H05K2201/09609 ,  H05K2201/09636 ,  H05K2201/09672 ,  H05K2203/0207

Abstract: The present invention provides a high speed signal fan-out method for BGA and a PCB using the same. The method comprises: providing a printed circuit board (PCB), providing a plurality of vias and signal traces of the vias on the PCB; and providing back-drilled holes for routing of other signal traces at positions corresponding to the vias. The vias are arranged into a plurality of straight lines from an edge to the center of the PCB. The plurality of straight lines each is horizontal or vertical. The signal traces of the vias in a straight line are arranged from high to low or from low to high with respect to routing positions of the vias, and the back-drilled holes of the plurality of vias are arranged in descending or ascending order corresponding to the depths of the back-drilled holes.

公开(公告)号：US09986634B2

公开(公告)日：2018-05-29

申请号：US15381301

申请日：2016-12-16

Applicant: Curtiss-Wright Controls, Inc.

Inventor： Michael Rose ,  Robert Sullivan

IPC: H05K1/02 ,  H05K3/40 ,  H05K3/20 ,  H05K1/11

CPC classification number: H05K1/0251 ,  H05K1/0216 ,  H05K1/024 ,  H05K1/0245 ,  H05K1/0298 ,  H05K1/115 ,  H05K3/20 ,  H05K3/4038 ,  H05K2201/0187 ,  H05K2201/09063 ,  H05K2201/09227 ,  H05K2201/09636 ,  H05K2201/09718 ,  H05K2201/1059

Abstract: A circuit board comprises a plurality of layers, first and second reference conductive vias extending in a vertical direction through at least a portion of the plurality of layers, first and second signal conductive vias extending in the vertical direction between and spaced apart in a horizontal direction from the first and second reference conductive vias through at least a portion of the plurality of layers, and a dielectric region extending in the vertical direction between the first and second signal conductive vias. An air via extends in the vertical direction through the dielectric region between the first and second signal conductive vias. An anti-pad extends in the horizontal direction between the first and second reference conductive vias and surrounding in the horizontal direction the first and second signal conductive vias, the air via, and the dielectric region.

公开(公告)号：US20160172734A1

公开(公告)日：2016-06-16

申请号：US14570791

申请日：2014-12-15

Applicant: Intel Corporation

Inventor： Min Wang ,  Russell N. Shryock

IPC: H01P3/08

CPC classification number: H05K1/0245 ,  H01P3/026 ,  H05K1/0251 ,  H05K1/116 ,  H05K2201/09636

Abstract: An interconnect topology is disclosed that includes a plurality of interconnections, each of which is coupled together using a via, where at least two of the vias are staggered with respect to each other. In one embodiment, the interconnect topology comprises a substrate, multiple signal traces routed through the substrate on multiple layers, and a plurality of vias, where each via couples a pair of the signal traces to form an interconnection between different ones of the multiple layers, and where a pair of vias comprise a first via to carry a positive differential signal via and a second via to carry a negative differential signal that are coupled to signal traces to form a differential signal pair. The differential first and second vias are staggered with respect to each other.

Abstract translation: 公开了一种互连拓扑，其包括多个互连，每个互连使用通孔耦合在一起，其中至少两个通孔相对于彼此交错。 在一个实施例中，互连拓扑包括衬底，通过多层上的衬底布线的多个信号迹线以及多个通孔，其中每个通孔耦合一对信号迹线以形成多个不同层之间的互连， 并且其中一对通孔包括第一通孔以承载正差分信号通路和第二通孔，以携带耦合到信号迹线的负差分信号以形成差分信号对。 差分第一和第二通孔相对于彼此交错。

公开(公告)号：US20160050754A1

公开(公告)日：2016-02-18

申请号：US14823519

申请日：2015-08-11

Applicant: FANUC Corporation

Inventor： Makoto BEKKE

IPC: H05K1/11

CPC classification number: H05K1/115 ,  H05K3/3447 ,  H05K2201/09545 ,  H05K2201/09609 ,  H05K2201/09636 ,  H05K2203/044

Abstract: A printed wiring board includes three or more than three through holes. An inner wall of the through hole is covered by conductive coating. Same size leads of an electronic component are inserted into the through holes. The through holes are soldered by dip soldering the printed wiring board in melting solder. The through holes have two or more diameters. The diameter of the through hole having more adjacent through holes is not larger than the diameter of the through hole having less adjacent through holes.

Abstract translation: 印刷电路板包括三个或三个以上的通孔。 通孔的内壁被导电涂层覆盖。 将电子部件的相同尺寸的引线插入到通孔中。 通孔通过浸焊焊接印刷线路板而熔化焊料来焊接通孔。 通孔具有两个或更多个直径。 具有更多相邻通孔的通孔的直径不大于具有较少相邻通孔的通孔的直径。

公开(公告)号：US20150114698A1

公开(公告)日：2015-04-30

申请号：US14105195

申请日：2013-12-13

Applicant: Tzu-Wei Huang ,  Chin-Sheng Wang

Inventor： Tzu-Wei Huang ,  Chin-Sheng Wang

IPC: H05K1/11 ,  H05K3/00 ,  H05K3/42 ,  H05K1/09

CPC classification number: H05K1/115 ,  H05K3/0094 ,  H05K3/421 ,  H05K2201/09509 ,  H05K2201/09563 ,  H05K2201/09636 ,  H05K2201/09854 ,  Y10T29/302

Abstract: A substrate structure includes a substrate and a filling material. The substrate has an upper surface, a lower surface, at least one first blind via and at least one second blind via. The substrate includes an insulation layer, a first copper foil layer and a second copper foil layer. The first copper foil layer and the second copper foil layer are respectively disposed on two opposite side surfaces of the insulation layer. The first blind via extends from the upper surface toward the second copper foil layer and exposes a portion of the second copper foil layer. The second blind via extends from the lower surface toward the first copper foil layer and exposes a portion of the first copper foil layer. The filling material is filled inside of the first blind via and the second blind via and covers the upper surface and the lower surface of the substrate.

Abstract translation: 衬底结构包括衬底和填充材料。 衬底具有上表面，下表面，至少一个第一盲孔和至少一个第二盲孔。 基板包括绝缘层，第一铜箔层和第二铜箔层。 第一铜箔层和第二铜箔层分别设置在绝缘层的两个相对的侧表面上。 第一盲孔从上表面延伸到第二铜箔层并暴露第二铜箔层的一部分。 第二盲孔从下表面延伸到第一铜箔层并暴露第一铜箔层的一部分。 填充材料填充在第一盲孔和第二盲孔内部并覆盖基板的上表面和下表面。