公开(公告)号：US11942378B2

公开(公告)日：2024-03-26

申请号：US17675961

申请日：2022-02-18

Applicant: Intel Corporation

Inventor： Han Wui Then ,  Marko Radosavljevic ,  Sansaptak Dasgupta

IPC: H01L29/778 ,  H01L21/8252 ,  H01L27/06 ,  H01L29/04 ,  H01L29/267 ,  H01L29/66 ,  H01L29/73

CPC classification number: H01L21/8252 ,  H01L27/0605 ,  H01L29/045 ,  H01L29/267 ,  H01L29/66462 ,  H01L29/73 ,  H01L29/778

Abstract: Techniques related to III-N transistors having improved performance, systems incorporating such transistors, and methods for forming them are discussed. Such transistors include first and second crystalline III-N material layers separated by an intervening layer other than a III-N material such that the first crystalline III-N material layer has a first crystal orientation that is inverted with respect to a second crystal orientation of the second crystalline III-N material layer.

公开(公告)号：US11728346B2

公开(公告)日：2023-08-15

申请号：US17501914

申请日：2021-10-14

Applicant: INTEL CORPORATION

Inventor： Marko Radosavljevic ,  Han Wui Then ,  Sansaptak Dasgupta

IPC: H01L27/092 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/20 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0924 ,  H01L21/823418 ,  H01L21/823431 ,  H01L29/0847 ,  H01L29/2003 ,  H01L29/66795 ,  H01L29/7851

Abstract: A device including a III-N material is described. In an example, the device has a terminal structure with a central body and a first plurality of fins, and a second plurality of fins, opposite the first plurality of fins. A polarization charge inducing layer including a III-N material in the terminal structure. A gate electrode is disposed above and on a portion of the polarization charge inducing layer. A source structure is on the polarization charge inducing layer and on sidewalls of the first plurality of fins. A drain structure is on the polarization charge inducing layer and on sidewalls of the second plurality of fins. The device further includes a source structure and a drain structure on opposite sides of the gate electrode and a source contact on the source structure and a drain contact on the drain structure.

公开(公告)号：US11715799B2

公开(公告)日：2023-08-01

申请号：US17526562

申请日：2021-11-15

Applicant: Intel Corporation

Inventor： Marko Radosavljevic ,  Sansaptak Dasgupta ,  Han Wui Then

IPC: H01L29/78 ,  H01L21/8238 ,  H01L21/8258 ,  H01L27/092 ,  H01L27/06 ,  H01L29/66 ,  H01L29/10 ,  H01L29/20

CPC classification number: H01L29/7851 ,  H01L21/8258 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0605 ,  H01L27/0924 ,  H01L29/1054 ,  H01L29/2003 ,  H01L29/66795

Abstract: Methods and apparatus to form silicon-based transistors on group III-nitride materials using aspect ratio trapping are disclosed. An example integrated circuit includes a group III-nitride substrate and a fin of silicon formed on the group III-nitride substrate. The integrated circuit further includes a first transistor formed on the fin of silicon and a second transistor formed on the group III-nitride substrate.

公开(公告)号：US11715791B2

公开(公告)日：2023-08-01

申请号：US16643930

申请日：2017-09-28

Applicant: Intel Corporation

Inventor： Marko Radosavljevic ,  Han Wui Then ,  Sansaptak Dasgupta ,  Kevin Lin ,  Paul Fischer

IPC: H01L29/778 ,  H01L27/12 ,  H01L29/20 ,  H01L29/66

CPC classification number: H01L29/7786 ,  H01L27/1203 ,  H01L29/2003 ,  H01L29/66462 ,  H01L29/7787

Abstract: A semiconductor-on-insulator (SOI) substrate with a compliant substrate layer advantageous for seeding an epitaxial III-N semiconductor stack upon which III-N devices (e.g., III-N HFETs) may be formed. The compliant layer may be (111) silicon, for example. The SOI substrate may further include another layer that may have one or more of lower electrical resistivity, greater thickness, or a different crystal orientation relative to the compliant substrate layer. A SOI substrate may include a (100) silicon layer advantageous for integrating Group IV devices (e.g., Si FETs), for example. To reduce parasitic coupling between an HFET and a substrate layer of relatively low electrical resistivity, one or more layers of the substrate may be removed within a region below the HFETs. Once removed, the resulting void may be backfilled with another material, or the void may be sealed, for example during back-end-of-line processing.

公开(公告)号：US11710765B2

公开(公告)日：2023-07-25

申请号：US17724152

申请日：2022-04-19

Applicant: Intel Corporation

Inventor： Marko Radosavljevic ,  Sansaptak Dasgupta ,  Han Wui Then

IPC: H01L49/02

CPC classification number: H01L28/91

Abstract: A method for forming non-planar capacitors of desired dimensions is disclosed. The method is based on providing a three-dimensional structure of a first material over a substrate, enclosing the structure with a second material that is sufficiently etch-selective with respect to the first material, and then performing a wet etch to remove most of the first material but not the second material, thus forming a cavity within the second material. Shape and dimensions of the cavity are comparable to those desired for the final non-planar capacitor. At least one electrode of a capacitor may then be formed within the cavity. Using the etch selectivity of the first and second materials advantageously allows applying wet etch techniques for forming high aspect ratio openings in fabricating non-planar capacitors, which is easier and more reliable than relying on dry etch techniques.

公开(公告)号：US11699704B2

公开(公告)日：2023-07-11

申请号：US16642356

申请日：2017-09-28

Applicant: Intel Corporation

Inventor： Van H. Le ,  Marko Radosavljevic ,  Han Wui Then ,  Willy Rachmady ,  Ravi Pillarisetty ,  Abhishek Sharma ,  Gilbert Dewey ,  Sansaptak Dasgupta

IPC: H01L27/092 ,  H01L21/8258 ,  H01L27/088 ,  H01L29/20 ,  H01L29/205 ,  H01L29/66 ,  H01L29/778 ,  H01L29/786

CPC classification number: H01L27/0922 ,  H01L21/8258 ,  H01L27/0883 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/66462 ,  H01L29/66969 ,  H01L29/7786 ,  H01L29/7869

Abstract: A semiconductor device comprising stacked complimentary transistors are described. In some embodiments, the semiconductor device comprises a first device comprising an enhancement mode III-N heterostructure field effect transistor (HFET), and a second device over the first device. In an example, the second device comprises a depletion mode thin film transistor. In an example, a connector is to couple a first terminal of the first device to a first terminal of the second device.

公开(公告)号：US11670686B2

公开(公告)日：2023-06-06

申请号：US16636760

申请日：2017-09-26

Applicant: Intel Corporation

Inventor： Marko Radosavljevic ,  Sansaptak Dasgupta ,  Han Wui Then

IPC: H01L29/20 ,  H01L21/02 ,  H01L29/66 ,  H01L29/778 ,  H01L29/775 ,  H01L29/78

CPC classification number: H01L29/2003 ,  H01L21/0254 ,  H01L21/02642 ,  H01L21/02647 ,  H01L29/775 ,  H01L29/7853 ,  H01L29/66462 ,  H01L29/7786 ,  H01L2029/7858

Abstract: A method for forming III-N structures of desired nanoscale dimensions is disclosed. The method is based on, first, providing a material to serve as a shell inside which a cavity can be formed, followed by using epitaxial growth to fill the cavity with III-N semiconductor(s). Filling a cavity of specified shape and dimensions with a III-N semiconductor results in formation of a III-N structure which has shape and dimensions defined by those of the cavity in the shell, advantageously enabling formation of III-N structures on a nanometer scale without having to rely on etching of III-N materials. Ensuring that at least a part of the III-N material in the cavity is formed by lateral epitaxial overgrowth allows obtaining high quality III-N semiconductor in that part without having to grow a thick layer. Disclosed III-N nanostructures can serve as foundation for fabricating III-N device components, e.g. III-N transistors, having non-planar architecture.

公开(公告)号：US11610971B2

公开(公告)日：2023-03-21

申请号：US16222976

申请日：2018-12-17

Applicant: Intel Corporation

Inventor： Sansaptak Dasgupta ,  Marko Radosavljevic ,  Han Wui Then ,  Nidhi Nidhi ,  Rahul Ramaswamy ,  Johann Rode ,  Paul Fischer ,  Walid Hafez

IPC: H01L29/205 ,  H01L29/10 ,  H01L29/778 ,  H01L29/20 ,  H01L21/02 ,  H01L29/66 ,  H01L21/762 ,  H01L29/08 ,  H01L29/423 ,  H01L29/207

Abstract: An integrated circuit structure comprises a base layer that includes a channel region, wherein the base layer and the channel region include group III-V semiconductor material. A polarization layer stack is over the base layer, wherein the polarization layer stack comprises a buffer stack, an interlayer over the buffer stack, a polarization layer over the interlayer. A cap layer stack is over the polarization layer to reduce transistor access resistance.

公开(公告)号：US11610887B2

公开(公告)日：2023-03-21

申请号：US16243523

申请日：2019-01-09

Applicant: Intel Corporation

Inventor： Han Wui Then ,  Marko Radosavljevic ,  Sansaptak Dasgupta ,  Paul B. Fischer ,  Walid M. Hafez

IPC: H01L27/092 ,  H01L29/20 ,  H01L29/205 ,  H01L29/778 ,  H01L29/423 ,  H01L21/8252 ,  H01L29/786 ,  H01L23/34 ,  H01L29/66

Abstract: Disclosed herein are IC structures, packages, and devices that include thin-film transistors (TFTs) integrated on the same substrate/die/chip as III-N transistors. An example IC structure includes an III-N semiconductor material provided over a support structure, a III-N transistor provided over a first portion of the III-N material, and a TFT provided over a second portion of the III-N material. Because the III-N transistor and the TFT are both provided over a single support structure, they may be referred to as “integrated” transistors. Because the III-N transistor and the TFT are provided over different portions of the III-N semiconductor material, and, therefore, over different portion of the support structure, their integration may be referred to as “side-by-side” integration. Integrating TFTs with III-N transistors may reduce costs and improve performance, e.g., by reducing losses incurred when power is routed off chip in a multi-chip package.

公开(公告)号：US20230073026A1

公开(公告)日：2023-03-09

申请号：US17470189

申请日：2021-09-09

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Kimin Jun ,  Shawna M. Liff ,  Johanna M. Swan ,  Han Wui Then

IPC: H01L23/528 ,  H01L23/522

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first die, having a first surface and an opposing second surface, in a first layer, and including a first metallization stack at the first surface; a device layer on the first metallization stack; a second metallization stack on the device layer; and an interconnect on the first surface of the die electrically coupled to the first metallization stack; a conductive pillar in the first layer; and a second die, having a first surface and an opposing second surface, in a second layer on the first layer, wherein the first surface of the second die is coupled to the conductive pillar and to the second surface of the first die by a hybrid bonding region.