公开(公告)号：US20190130635A1

公开(公告)日：2019-05-02

申请号：US16233610

申请日：2018-12-27

Applicant: Intel Corporation

Inventor： Murali Ramadoss ,  Balaji Vembu ,  Hema C. Nalluri ,  Michael Apodaca ,  Jeffery S. Boles

IPC: G06T15/80 ,  G06F9/48 ,  G06T1/20

Abstract: By scheduling/managing workload submission to a POSH pipe one can exploit parallelism with minimum impact to the software scheduler in some embodiments.

公开(公告)号：US10242486B2

公开(公告)日：2019-03-26

申请号：US15488837

申请日：2017-04-17

Applicant: Intel Corporation

Inventor： Chandrasekaran Sakthivel ,  Michael Apodaca ,  Kai Xiao ,  Altug Koker ,  Jeffery S. Boles ,  Adam T. Lake ,  Nikos Kaburlasos ,  Joydeep Ray ,  John H. Feit ,  Travis T. Schluessler ,  Jacek Kwiatkowski ,  James M. Holland ,  Prasoonkumar Surti ,  Jonathan Kennedy ,  Louis Feng ,  Barnan Das ,  Narayan Biswal ,  Stanley J. Baran ,  Gokcen Cilingir ,  Nilesh V. Shah ,  Archie Sharma ,  Mayuresh M. Varerkar

IPC: G06T15/06 ,  G06T15/00 ,  G06T19/00 ,  G06F3/01 ,  H04S7/00 ,  G06T15/04 ,  G06T15/80 ,  G06T17/10

Abstract: Systems, apparatuses and methods may provide away to render augmented reality and virtual reality (VR/AR) environment information. More particularly, systems, apparatuses and methods may provide a way to selectively suppress and enhance VR/AR renderings of n-dimensional environments. The systems, apparatuses and methods may deepen a user's VR/AR experience by focusing on particular feedback information, while suppressing other feedback information from the environment.

公开(公告)号：US20190087983A1

公开(公告)日：2019-03-21

申请号：US16142866

申请日：2018-09-26

Applicant: Intel Corporation

Inventor： Karthik Vaidyanathan ,  Prasoonkumar Surti ,  Hugues Labbe ,  Atsuo Kuwahara ,  Sameer Kp ,  Jonathan Kennedy ,  Murali Ramadoss ,  Michael Apodaca ,  Abhishek Venkatesh

IPC: G06T11/00 ,  G06T1/60 ,  G06T15/00 ,  G06T1/20

CPC classification number: G06T11/001 ,  G06T1/20 ,  G06T1/60 ,  G06T15/005 ,  G06T2210/52

Abstract: Systems, apparatuses and methods may provide for technology that determines a stencil value and uses the stencil value to control, via a stencil buffer, a coarse pixel size of a graphics pipeline. Additionally, the stencil value may include a first range of bits defining a first dimension of the coarse pixel size and a second range of bits defining a second dimension of the coarse pixel size. In one example, the coarse pixel size is controlled for a plurality of pixels on a per pixel basis.

公开(公告)号：US10204394B2

公开(公告)日：2019-02-12

申请号：US15483837

申请日：2017-04-10

Applicant: Intel Corporation

Inventor： Abhishek Venkatesh ,  Karthik Vaidyanathan ,  Murali Ramadoss ,  Michael Apodaca ,  Prasoonkumar Surti

IPC: G06T1/20 ,  G06T1/60

Abstract: An embodiment of a graphics command coordinator apparatus may include a commonality identifier to identify a commonality between a first graphics command corresponding to a first frame and a second graphics command corresponding to a second frame, a commonality analyzer communicatively coupled to the commonality identifier to determine if the first graphics command and the second graphics command can be processed together based on the commonality identified by the commonality identifier, and a commonality indicator communicatively coupled to the commonality analyzer to provide an indication that the first graphics command and the second graphics command are to be processed together. Other embodiments are disclosed and claimed.

公开(公告)号：US10192351B2

公开(公告)日：2019-01-29

申请号：US15488641

申请日：2017-04-17

Applicant: Intel Corporation

Inventor： Prasoonkumar Surti ,  Karthik Vaidyanathan ,  Murali Ramadoss ,  Michael Apodaca ,  Abhishek Venkatesh ,  Joydeep Ray ,  Abhishek R. Appu

IPC: G06T15/50 ,  G06T15/80 ,  G06T17/20 ,  G06T7/13 ,  G06T7/136 ,  G06T15/00

Abstract: Systems, apparatuses and methods may provide away to render edges of an object defined by multiple tessellation triangles. More particularly, systems, apparatuses and methods may provide a way to perform anti-aliasing at the edges of the object based on a coarse pixel rate, where the coarse pixels may be based on a coarse Z value indicate a resolution or granularity of detail of the coarse pixel. The systems, apparatuses and methods may use a shader dispatch engine to dispatch raster rules to a pixel shader to direct the pixel shader to include, in a tile and/or tessellation triangle, one more finer coarse pixels based on a percent of coverage provided by a finer coarse pixel of a tessellation triangle at or along the edge of the object.

公开(公告)号：US10068307B2

公开(公告)日：2018-09-04

申请号：US15159897

申请日：2016-05-20

Applicant: Intel Corporation

Inventor： Balaji Vembu ,  Peter L. Doyle ,  Michael Apodaca ,  Hema C. Nalluri ,  Jeffery S. Boles

IPC: G06T15/40 ,  G06T1/20 ,  G06T15/00 ,  G06T15/80 ,  G06T1/60

Abstract: The same set of render commands can be re-executed for each of a plurality of tiles making up a graphic scene to be rendered. Each time the list of commands is executed, the way the commands are executed may be modified based on information received from tile pre-processing. Specifically, a jump if command may be inserted into the command list. When this command is encountered, a determination is made, based on information received from tile pre-processing pipeline, whether to execute the command for the next primitive or not. If the next primitive is to be culled then the command for the next primitive is not executed and the flow moves past that command. If the next primitive is to be executed then the jump is not implemented. This enables avoiding reloading the same list of commands over and over for every tile.

公开(公告)号：US20240161356A1

公开(公告)日：2024-05-16

申请号：US18517318

申请日：2023-11-22

Applicant: Intel Corporation

Inventor： Karthik Vaidyanathan ,  Prasoonkumar Surti ,  Hugues Labbe ,  Atsuo Kuwahara ,  Sameer KP ,  Jonathan Kennedy ,  Murali Ramadoss ,  Michael Apodaca ,  Abhishek Venkatesh

IPC: G06T11/00 ,  G06T1/20 ,  G06T1/60 ,  G06T15/00

CPC classification number: G06T11/001 ,  G06T1/20 ,  G06T1/60 ,  G06T15/005 ,  G06T2210/52

Abstract: Systems, apparatuses and methods may provide for technology that determines a stencil value and uses the stencil value to control, via a stencil buffer, a coarse pixel size of a graphics pipeline. Additionally, the stencil value may include a first range of bits defining a first dimension of the coarse pixel size and a second range of bits defining a second dimension of the coarse pixel size. In one example, the coarse pixel size is controlled for a plurality of pixels on a per pixel basis.

公开(公告)号：US11915459B2

公开(公告)日：2024-02-27

申请号：US17740754

申请日：2022-05-10

Applicant: INTEL CORPORATION

Inventor： Carson Brownlee ,  Carsten Benthin ,  Joshua Barczak ,  Kai Xiao ,  Michael Apodaca ,  Prasoonkumar Surti ,  Thomas Raoux

IPC: G06T9/40 ,  G06T15/06 ,  G06T15/20 ,  G06T1/60

CPC classification number: G06T9/40 ,  G06T1/60 ,  G06T15/06 ,  G06T15/20 ,  G06T2210/21

Abstract: Apparatus and method for context-aware compression. For example, one embodiment of an apparatus comprises: ray traversal/intersection circuitry to traverse rays through a hierarchical acceleration data structure to identify intersections between rays and primitives of a graphics scene; matrix compression circuitry/logic to compress hierarchical transformation matrices to generate compressed hierarchical transformation matrices by quantizing N-bit floating point data elements associated with child transforms of the hierarchical transformation matrices to variable-bit floating point numbers or integers comprising offsets from a parent transform of the child transform; and an instance processor to generate a plurality of instances of one or more base geometric objects in accordance with the compressed hierarchical transformation matrices.

公开(公告)号：US11750787B2

公开(公告)日：2023-09-05

申请号：US17526633

申请日：2021-11-15

Applicant: Intel Corporation

Inventor： Mayuresh Varerkar ,  Stanley Baran ,  Michael Apodaca ,  Prasoonkumar Surti ,  Atsuo Kuwahara ,  Narayan Biswal ,  Jill Boyce ,  Yi-Jen Chiu ,  Gokcen Cilingir ,  Barnan Das ,  Atul Divekar ,  Srikanth Potluri ,  Nilesh Shah ,  Archie Sharma

IPC: H04H60/33 ,  H04N13/111 ,  H04N19/597 ,  G06F9/38 ,  G06F3/01 ,  G06N20/00

CPC classification number: H04N13/111 ,  G06F3/012 ,  G06F9/3877 ,  G06N20/00 ,  H04N19/597

Abstract: A mechanism is described for facilitating adaptive resolution and viewpoint-prediction for immersive media in computing environments. An apparatus of embodiments, as described herein, includes one or more processors to receive viewing positions associated with a user with respect to a display, and analyze relevance of media contents based on the viewing positions, where the media content includes immersive videos of scenes captured by one or more cameras. The one or more processors are further to predict portions of the media contents as relevant portions based on the viewing positions and transmit the relevant portions to be rendered and displayed.

公开(公告)号：US11568591B2

公开(公告)日：2023-01-31

申请号：US16996208

申请日：2020-08-18

Applicant: INTEL CORPORATION

Inventor： Karthik Vaidyanathan ,  Michael Apodaca ,  Thomas Raoux ,  Carsten Benthin ,  Kai Xiao ,  Carson Brownlee ,  Joshua Barczak

IPC: G06T15/06 ,  G06T1/60 ,  G06T5/00 ,  G06T9/00

Abstract: An apparatus and method to execute ray tracing instructions. For example, one embodiment of an apparatus comprises execution circuitry to execute a dequantize instruction to convert a plurality of quantized data values to a plurality of dequantized data values, the dequantize instruction including a first source operand to identify a plurality of packed quantized data values in a source register and a destination operand to identify a destination register in which to store a plurality of packed dequantized data values, wherein the execution circuitry is to convert each packed quantized data value in the source register to a floating point value, to multiply the floating point value by a first value to generate a first product and to add the first product to a second value to generate a dequantized data value, and to store the dequantized data value in a packed data element location in the destination register.