公开(公告)号：US20160211331A1

公开(公告)日：2016-07-21

申请号：US15083423

申请日：2016-03-29

Applicant: Sensor Electronic Technology, Inc.

Inventor： Maxim S. Shatalov ,  Jinwei Yang ,  Wenhong Sun ,  Rakesh Jain ,  Michael Shur ,  Remigijus Gaska

IPC: H01L29/15 ,  H01L29/20 ,  H01L29/06 ,  H01L29/205

CPC classification number: H01L29/158 ,  H01L21/0237 ,  H01L21/02458 ,  H01L21/02505 ,  H01L21/02507 ,  H01L21/02513 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/0265 ,  H01L29/0657 ,  H01L29/2003 ,  H01L29/205 ,  H01L33/007 ,  H01L33/12

Abstract: A semiconductor structure, such as a group III nitride-based semiconductor structure is provided. The semiconductor structure includes a cavity containing semiconductor layer. The cavity containing semiconductor layer can have a thickness greater than two monolayers and a multiple cavities. The cavities can have a characteristic size of at least one nanometer and a characteristic separation of at least five nanometers.

Abstract translation: 提供了诸如III族氮化物基半导体结构的半导体结构。 半导体结构包括含有半导体层的空腔。 含腔的半导体层可以具有大于两个单层和多个空腔的厚度。 空腔可以具有至少一纳米的特征尺寸和至少五纳米的特征分离。

公开(公告)号：US20160172544A1

公开(公告)日：2016-06-16

申请号：US15042433

申请日：2016-02-12

Applicant: Sensor Electronic Technology, Inc.

Inventor： Remigijus Gaska ,  Maxim S. Shatalov ,  Alexander Dobrinsky ,  Jinwei Yang ,  Michael Shur ,  Grigory Simin

IPC: H01L33/40 ,  H01L33/32 ,  H01L33/22 ,  H01L33/00 ,  H01L33/06

CPC classification number: H01L33/405 ,  H01L24/05 ,  H01L33/007 ,  H01L33/0095 ,  H01L33/06 ,  H01L33/22 ,  H01L33/32 ,  H01L33/38 ,  H01L2224/0401 ,  H01L2224/06102 ,  H01L2224/1134 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2933/0016 ,  H01L2924/00

Abstract: A device including a first semiconductor layer and a contact to the first semiconductor layer is disclosed. An interface between the first semiconductor layer and the contact includes a first roughness profile having a characteristic height and a characteristic width. The characteristic height can correspond to an average vertical distance between crests and adjacent valleys in the first roughness profile. The characteristic width can correspond to an average lateral distance between the crests and adjacent valleys in the first roughness profile.

Abstract translation: 公开了一种包括第一半导体层和与第一半导体层的接触的器件。 第一半导体层和触点之间的界面包括具有特征高度和特征宽度的第一粗糙度轮廓。 特征高度可以对应于第一粗糙度轮廓中波峰和相邻谷之间的平均垂直距离。 特征宽度可以对应于第一粗糙度轮廓中的波峰和相邻谷之间的平均横向距离。

公开(公告)号：US20160118534A1

公开(公告)日：2016-04-28

申请号：US14984342

申请日：2015-12-30

Applicant: Sensor Electronic Technology, Inc.

Inventor： Michael Shur ,  Rakesh Jain ,  Maxim S. Shatalov ,  Alexander Dobrinsky ,  Jinwei Yang ,  Remigijus Gaska ,  Mikhail Gaevski

IPC: H01L33/06 ,  H01L33/38 ,  H01L33/00 ,  H01L33/32

CPC classification number: H01L33/06 ,  H01L33/007 ,  H01L33/18 ,  H01L33/30 ,  H01L33/32 ,  H01L33/382 ,  H01L2224/14 ,  H01L2933/0016 ,  H01S5/3209 ,  H01S5/3413 ,  H01S5/34333

Abstract: A device comprising a semiconductor layer including a plurality of compositional inhomogeneous regions is provided. The difference between an average band gap for the plurality of compositional inhomogeneous regions and an average band gap for a remaining portion of the semiconductor layer can be at least thermal energy. Additionally, a characteristic size of the plurality of compositional inhomogeneous regions can be smaller than an inverse of a dislocation density for the semiconductor layer.

公开(公告)号：US09287455B2

公开(公告)日：2016-03-15

申请号：US14184741

申请日：2014-02-20

Applicant: Sensor Electronic Technology, Inc.

Inventor： Michael Shur ,  Remigijus Gaska ,  Jinwei Yang

IPC: H01L33/04 ,  H01L33/32 ,  H01L33/06 ,  H01L33/02 ,  H01L33/14 ,  H01L33/10

CPC classification number: H01L33/325 ,  H01L33/025 ,  H01L33/04 ,  H01L33/06 ,  H01L33/10 ,  H01L33/14

Abstract: A carbon doped short period superlattice is provided. A heterostructure includes a short period superlattice comprising a plurality of quantum wells alternating with a plurality of barriers. One or more of the quantum wells and/or the barriers includes a carbon doped layer (e.g., a non-percolated or percolated carbon atomic plane).

Abstract translation: 提供了碳掺杂短周期超晶格。 异质结构包括短周期超晶格，其包括与多个势垒交替的多个量子阱。 量子阱和/或势垒中的一个或多个包括碳掺杂层（例如，非过滤或质子交换的碳原子平面）。

公开(公告)号：US09287442B2

公开(公告)日：2016-03-15

申请号：US13803753

申请日：2013-03-14

Applicant: Sensor Electronic Technology, Inc.

Inventor： Maxim S Shatalov ,  Remigijus Gaska ,  Jinwei Yang ,  Michael Shur ,  Alexander Dobrinsky

IPC: H01L33/06 ,  H01L33/00 ,  B82Y10/00 ,  B82Y20/00 ,  H01L29/20 ,  H01L29/201 ,  H01L29/15 ,  H01L29/205 ,  H01L33/32 ,  H01L33/04 ,  H01S5/20 ,  H01S5/32 ,  H01S5/343 ,  H01S5/34

CPC classification number: H01L33/06 ,  B82Y10/00 ,  B82Y20/00 ,  H01L29/155 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/205 ,  H01L33/0075 ,  H01L33/04 ,  H01L33/32 ,  H01S5/2009 ,  H01S5/3211 ,  H01S5/3216 ,  H01S5/3407 ,  H01S5/34333

Abstract: A solution for designing and/or fabricating a structure including a quantum well and an adjacent barrier is provided. A target band discontinuity between the quantum well and the adjacent barrier is selected to coincide with an activation energy of a dopant for the quantum well and/or barrier. For example, a target valence band discontinuity can be selected such that a dopant energy level of a dopant in the adjacent barrier coincides with a valence energy band edge for the quantum well and/or a ground state energy for free carriers in a valence energy band for the quantum well. Additionally, a target doping level for the quantum well and/or adjacent barrier can be selected to facilitate a real space transfer of holes across the barrier. The quantum well and the adjacent barrier can be formed such that the actual band discontinuity and/or actual doping level(s) correspond to the relevant target(s).

Abstract translation: 提供了一种用于设计和/或制造包括量子阱和相邻屏障的结构的解决方案。 选择量子阱和相邻屏障之间的目标频带不连续性以与量子阱和/或屏障的掺杂剂的活化能一致。 例如，可以选择目标价带不连续性，使得相邻势垒中的掺杂剂的掺杂剂能级与量子阱的价态能带边缘和/或价态能带中的自由载流子的基态能量一致 量子阱。 另外，可以选择量子阱和/或相邻势垒的目标掺杂水平以促进穿过势垒的空穴的实际空间传递。 可以形成量子阱和相邻势垒，使得实际的带不连续性和/或实际掺杂水平对应于相关目标。

公开(公告)号：US20160035936A1

公开(公告)日：2016-02-04

申请号：US14822508

申请日：2015-08-10

Applicant: SENSOR ELECTRONIC TECHNOLOGY, INC.

Inventor： Rakesh Jain ,  Wenhong Sun ,  Jinwei Yang ,  Maxim S. Shatalov ,  Alexander Dobrinsky ,  Michael Shur ,  Remigijus Gaska

IPC: H01L33/12 ,  H01L33/24 ,  H01L33/32 ,  H01L33/18 ,  H01L33/22

CPC classification number: H01L33/12 ,  C30B25/04 ,  C30B25/183 ,  C30B29/406 ,  H01L21/0242 ,  H01L21/0243 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02639 ,  H01L21/0265 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/518 ,  H01L29/7786 ,  H01L29/7787 ,  H01L33/06 ,  H01L33/10 ,  H01L33/145 ,  H01L33/22 ,  H01L33/24 ,  H01L33/32 ,  H01L33/405 ,  H01L2933/0091

Abstract: A method of fabricating a device using a layer with a patterned surface for improving the growth of semiconductor layers, such as group III nitride-based semiconductor layers with a high concentration of aluminum, is provided. The patterned surface can include a substantially flat top surface and a plurality of stress reducing regions, such as openings. The substantially flat top surface can have a root mean square roughness less than approximately 0.5 nanometers, and the stress reducing regions can have a characteristic size between approximately 0.1 microns and approximately five microns and a depth of at least 0.2 microns. A layer of group-III nitride material can be grown on the first layer and have a thickness at least twice the characteristic size of the stress reducing regions. A device including one or more of these features also is provided.

Abstract translation: 提供了使用具有图案化表面的层以改善半导体层生长的器件的方法，例如具有高浓度铝的III族氮化物基半导体层。 图案化表面可以包括基本上平坦的顶表面和多个减压区域，例如开口。 基本上平坦的顶表面可以具有小于约0.5纳米的均方根粗糙度，并且应力减小区域可以具有在约0.1微米至约5微米之间的特征尺寸和至少0.2微米的深度。 III族氮化物材料层可以在第一层上生长并且具有至少是应力减小区域的特征尺寸的两倍的厚度。 还提供了包括这些特征中的一个或多个的装置。

公开(公告)号：US20150372193A1

公开(公告)日：2015-12-24

申请号：US13647885

申请日：2012-10-09

Applicant: Sensor Electronic Technology, Inc.

Inventor： Rakesh Jain ,  Wenhong Sun ,  Jinwei Yang ,  Maxim S. Shatalov ,  Alexander Dobrinsky ,  Michael Shur ,  Remigijus Gaska

IPC: H01L33/22 ,  H01L33/12 ,  H01L29/34 ,  H01L29/20 ,  H01L29/778 ,  H01L33/32 ,  H01L33/24

CPC classification number: H01L33/22 ,  H01L21/0242 ,  H01L21/0243 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02639 ,  H01L21/0265 ,  H01L21/02658 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/34 ,  H01L29/66462 ,  H01L29/778 ,  H01L29/7787 ,  H01L33/007 ,  H01L33/06 ,  H01L33/10 ,  H01L33/12 ,  H01L33/24 ,  H01L33/32 ,  H01L2933/0091

Abstract: A device having a layer with a patterned surface for improving the growth of semiconductor layers, such as group III nitride-based semiconductor layers with a high concentration of aluminum, is provided. The patterned surface can include a substantially flat top surface and a plurality of stress reducing regions, such as openings. The substantially flat top surface can have a root mean square roughness less than approximately 0.5 nanometers, and the stress reducing regions can have a characteristic size between approximately 0.1 microns and approximately five microns and a depth of at least 0.2 microns. A layer of group-III nitride material can be grown on the first layer and have a thickness at least twice the characteristic size of the stress reducing regions.

Abstract translation: 提供具有具有用于改善半导体层的生长的图案化表面的层的器件，例如具有高浓度铝的III族氮化物基半导体层。 图案化表面可以包括基本上平坦的顶表面和多个减压区域，例如开口。 基本上平坦的顶表面可以具有小于约0.5纳米的均方根粗糙度，并且应力减小区域可以具有在约0.1微米至约5微米之间的特征尺寸和至少0.2微米的深度。 III族氮化物材料层可以在第一层上生长并且具有至少是应力减小区域的特征尺寸的两倍的厚度。

公开(公告)号：US20150207029A1

公开(公告)日：2015-07-23

申请号：US14675596

申请日：2015-03-31

Applicant: SENSOR ELECTRONIC TECHNOLOGY, INC.

Inventor： Michael Shur ,  Remigijus Gaska ,  Jinwei Yang ,  Alexander Dobrinsky

IPC: H01L33/06 ,  H01L33/14 ,  H01L33/00

CPC classification number: H01L33/06 ,  H01L33/0045 ,  H01L33/18 ,  H01L33/32

Abstract: A superlattice layer including a plurality of periods, each of which is formed from a plurality of sub-layers is provided. Each sub-layer comprises a different composition than the adjacent sub-layer(s) and comprises a polarization that is opposite a polarization of the adjacent sub-layer(s). In this manner, the polarizations of the respective adjacent sub-layers compensate for one another. Furthermore, the superlattice layer can be configured to be at least partially transparent to radiation, such as ultraviolet radiation.

Abstract translation: 提供包括多个周期的超晶格层，每个周期由多个子层形成。 每个子层包括与相邻子层不同的组成，并且包括与相邻子层的极化相反的极化。 以这种方式，各相邻子层的极化相互补偿。 此外，超晶格层可被配置为对诸如紫外线辐射的辐射至少部分透明。

公开(公告)号：US09087695B2

公开(公告)日：2015-07-21

申请号：US14060173

申请日：2013-10-22

Applicant: Sensor Electronic Technology, Inc.

Inventor： Igor Agafonov ,  Jinwei Yang ,  Michael Shur ,  Remigijus Gaska

IPC: H01L21/00 ,  H01L21/02 ,  C23C16/455 ,  C23C16/458 ,  C23C16/52 ,  H01L21/66

CPC classification number: H01L21/0262 ,  C23C16/455 ,  C23C16/4584 ,  C23C16/52 ,  H01L22/12 ,  H01L22/26 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A solution for manufacturing semiconductors is provided. An embodiment provides a chemical vapor deposition reactor, which includes a chemical vapor deposition chamber. A substrate holder located in the chemical vapor deposition chamber can be rotated about its own axis at a first angular speed, and a gas injection component located in the chemical vapor deposition chamber can be rotated about an axis of the gas injection component at a second angular speed. The angular speeds are independently selectable and can be configured to cause each point on a surface of a substrate wafer to travel in an epicyclical trajectory within a gas flow injected by the gas injection component. An angle between the substrate holder axis and the gas injection component axis and/or a distance between the substrate holder axis and the gas injection component axis can be controlled variables.

Abstract translation: 提供制造半导体的解决方案。 实施例提供了一种化学气相沉积反应器，其包括化学气相沉积室。 位于化学气相沉积室中的衬底保持器可以以其第一角速度围绕其自身的轴线旋转，并且位于化学气相沉积室中的气体注入组件可以围绕气体注入部件的轴线以第二角度 速度。 角速度是可独立选择的，并且可以被配置成使得衬底晶片的表面上的每个点在由气体注入部件注入的气流中的行星轨迹中行进。 衬底保持器轴线和气体注入部件轴线之间的角度和/或衬底保持器轴线和气体注入部件轴线之间的距离可以是受控变量。

公开(公告)号：US09042420B2

公开(公告)日：2015-05-26

申请号：US14531162

申请日：2014-11-03

Applicant: Sensor Electronic Technology, Inc.

Inventor： Michael Shur ,  Maxim S. Shatalov ,  Alexander Dobrinsky ,  Remigijus Gaska ,  Jinwei Yang

IPC: H01S3/14 ,  H01S5/00 ,  H01L33/00 ,  H01L33/06 ,  H01L33/32 ,  H01S5/32 ,  H01S5/34

CPC classification number: H01L33/0025 ,  B82Y10/00 ,  H01L21/0237 ,  H01L21/02458 ,  H01L21/02507 ,  H01L21/02518 ,  H01L21/0254 ,  H01L29/15 ,  H01L29/2003 ,  H01L29/778 ,  H01L33/06 ,  H01L33/32 ,  H01S5/0421 ,  H01S5/3216 ,  H01S5/342 ,  H01S5/34333

Abstract: A device including one or more layers with lateral regions configured to facilitate the transmission of radiation through the layer and lateral regions configured to facilitate current flow through the layer is provided. The layer can comprise a short period superlattice, which includes barriers alternating with wells. In this case, the barriers can include both transparent regions, which are configured to reduce an amount of radiation that is absorbed in the layer, and higher conductive regions, which are configured to keep the voltage drop across the layer within a desired range.

Abstract translation: 提供了一种包括一个或多个具有横向区域的层，该层被配置为有助于辐射通过该层的传输和被配置为促进流过该层的电流的横向区域。 该层可以包括短期超晶格，其包括与井交替的障碍物。 在这种情况下，障碍物可以包括被配置为减少在层中吸收的辐射量的透明区域以及被配置为将跨越层的电压降保持在期望范围内的较高导电区域。