公开(公告)号：US20240266435A1

公开(公告)日：2024-08-08

申请号：US18120980

申请日：2023-03-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ming-Hua Tsai ,  Chin-Chia Kuo ,  Wei-Hsuan Chang

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7835 ,  H01L29/6659

Abstract: A transistor with an embedded insulating structure set includes a substrate. A gate is disposed on the substrate. A first lightly doped region is disposed at one side of the gate. A second lightly doped region is disposed at another side of the gate. The first lightly doped region and the second lightly doped region have the same conductive type. The first lightly doped region is symmetrical to the second lightly doped region. A first source/drain doped region is disposed within the first lightly doped region. A second source/drain doped region is disposed within the second lightly doped region. A first insulating structure set is disposed within the first lightly doped region and the first source/drain doped region. The first insulating structure set includes an insulating block embedded within the substrate. A sidewall of the insulating block contacts the gate dielectric layer.

公开(公告)号：US20240266393A1

公开(公告)日：2024-08-08

申请号：US18119797

申请日：2023-03-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： CHUNYUAN QI ,  XINGXING CHEN ,  ZHUONA MA ,  HUI LIU

IPC: H01L29/06 ,  H01L21/308 ,  H01L27/12 ,  H01L29/16

CPC classification number: H01L29/0657 ,  H01L21/3086 ,  H01L27/1203 ,  H01L29/1604

Abstract: A metasurface structure includes a substrate having a first region and a second region not overlapping with the first region; a first pillar element within the first region on the substrate; and a second pillar element within the second region on the substrate. The first pillar element has a first sectional profile and the second pillar element has a second sectional profile that is different from the first sectional profile. At least one of the first sectional profile and the second sectional profile is of a non-rectangular shape.

公开(公告)号：US12057483B2

公开(公告)日：2024-08-06

申请号：US18078057

申请日：2022-12-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ming-Hua Tsai ,  Jung Han ,  Ming-Chi Li ,  Chih-Mou Lin ,  Yu-Hsiang Hung ,  Yu-Hsiang Lin ,  Tzu-Lang Shih

IPC: H01L29/423 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/42368 ,  H01L29/0607 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

Abstract: A semiconductor device includes a semiconductor substrate, a first gate oxide layer, and a first source/drain doped region. The first gate oxide layer is disposed on the semiconductor substrate, and the first gate oxide layer includes a main portion and an edge portion having a sloping sidewall. The first source/drain doped region is disposed in the semiconductor substrate and located adjacent to the edge portion of the first gate oxide layer. The first source/drain doped region includes a first portion and a second portion. The first portion is disposed under the edge portion of the first gate oxide layer in a vertical direction, and the second portion is connected with the first portion.

公开(公告)号：US12057401B2

公开(公告)日：2024-08-06

申请号：US18226784

申请日：2023-07-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Cheng Chen ,  Li-Hsuan Ho ,  Tsuo-Wen Lu ,  Shih-Hao Liang ,  Tsung-Hsun Wu ,  Po-Jen Chuang ,  Chi-Mao Hsu

IPC: H01L23/535 ,  H01L21/28 ,  H01L21/8238 ,  H01L23/528 ,  H01L27/02 ,  H01L27/092 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66

CPC classification number: H01L23/535 ,  H01L21/28088 ,  H01L21/82385 ,  H01L21/823871 ,  H01L23/528 ,  H01L27/092 ,  H01L29/4966 ,  H01L29/66545

Abstract: A semiconductor device including a substrate having a NMOS region and a PMOS region; a metal gate extending continuously along a first direction from the NMOS region to the PMOS region on the substrate; a first source/drain region extending along a second direction adjacent to two sides of the metal gate on the NMOS region; a second source/drain region extending along the second direction adjacent to two sides of the metal gate on the PMOS region; a first contact plug landing on the second source/drain region adjacent to one side of the metal gate; a second contact plug landing on the second source/drain region adjacent to another side of the metal gate; and a third contact plug landing directly on a portion of the metal gate on the PMOS region and between the first contact plug and the second contact plug.

公开(公告)号：US12057346B2

公开(公告)日：2024-08-06

申请号：US18243096

申请日：2023-09-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Chih Chang ,  Yuan-Fu Ko ,  Chih-Sheng Chang

IPC: H01L21/768 ,  H01L21/02 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L21/7682 ,  H01L21/02164 ,  H01L21/0217 ,  H01L23/528 ,  H01L23/53295

Abstract: A method for fabricating semiconductor device includes the steps of: forming a first inter-metal dielectric (IMD) layer on a substrate; forming a first metal interconnection in the first IMD layer; removing part of the first IMD layer; forming a spacer adjacent to the first metal interconnection; forming a second IMD layer on the spacer and the first metal interconnection; and forming a second metal interconnection in the second IMD layer and on the spacer and the first metal interconnection.

公开(公告)号：US12055849B2

公开(公告)日：2024-08-06

申请号：US17363380

申请日：2021-06-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Sheng-Lun Tseng ,  Yen-Ting Pan ,  Chih-Wei Hsu

IPC: G03F1/36 ,  G03F7/00 ,  H01L21/027

CPC classification number: G03F1/36 ,  G03F7/70441 ,  H01L21/0274

Abstract: A method for correcting a semiconductor mask pattern includes steps as follows: A pattern to be corrected in the semiconductor mask pattern is divided into a plurality of sub-blocks that are symmetrical to and coincide with each other. Then, an optical proximity correction (OPC) step is performed on one of the plurality of sub-blocks to obtain a modified template. At least one copy template is generated according to the modified template corresponding to the other ones of the plurality of sub-blocks. The modified template and the at least one copy template are spliced to form a correcting pattern to replace the original pattern to be corrected.

公开(公告)号：US20240260198A1

公开(公告)日：2024-08-01

申请号：US18113767

申请日：2023-02-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zheng-Yang LI ,  Li-Hsin YANG ,  Ming-Tung WANG ,  Shu-Mei FANG ,  Chia-Chan TSAI

IPC: H05K3/00 ,  G06T5/20

CPC classification number: H05K3/0008 ,  G06T5/20 ,  H05K2203/166

Abstract: An equipment automatic alignment method and a process robot device using the same are provided. The equipment automatic alignment method includes following steps. An image of an equipment is obtained. The image is enhanced to obtain a plurality of candidate patterns. Each of the candidate patterns is expanded to obtain a first rectangular block and a second rectangular block. A plurality of first target patterns are obtained according to the first rectangular block, and a plurality of second target patterns are obtained according to the second rectangular block. A first base point is obtained from the first target patterns, and a second base point is obtained from the second target patterns. An operation command is generated according to the first base point and the second base point to automatically control an operation interface of the equipment, so that the first base point is aligned with the second base point.

公开(公告)号：US20240258379A1

公开(公告)日：2024-08-01

申请号：US18632275

申请日：2024-04-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Hua Chang ,  Jian-Feng Li ,  Hsiang-Chieh Yen

IPC: H01L29/15 ,  H01L21/02 ,  H01L21/306 ,  H01L29/20 ,  H01L29/205 ,  H01L29/66 ,  H01L29/778

CPC classification number: H01L29/157 ,  H01L21/02458 ,  H01L21/02507 ,  H01L21/0254 ,  H01L21/30625 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/66462 ,  H01L29/7786

Abstract: The present disclosure provides a semiconductor device, the semiconductor device including a substrate, a nucleation layer, a buffer layer, an active layer and a gate electrode. The nucleation layer is disposed on the substrate, and the buffer layer is disposed on the nucleation layer, wherein the buffer layer includes a first superlattice layer having at least two heteromaterials alternately arranged in a horizontal direction, and a second superlattice layer having at least two heteromaterials vertically stacked along a vertical direction. The at least two heteromaterials stack at least once within the second superlattice layer. The active layer is disposed on the buffer layer, and the gate electrode is disposed on the active layer.

公开(公告)号：US20240256911A1

公开(公告)日：2024-08-01

申请号：US18123531

申请日：2023-03-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yan-Hsiu LIU ,  Pin-Yen TSAI

IPC: G06N5/022 ,  G06F18/2415

CPC classification number: G06N5/022 ,  G06F18/2415

Abstract: A method and a device for establishing a weak pattern severity model are provided. The method for establishing the weak pattern severity model includes the following steps. A plurality of weak patterns are obtained. A plurality of experiments are performed on each of the weak patterns with a plurality of parameter setting values of at least one process parameter to obtain a plurality of experimental results. According to the experimental results, a plurality of defects are obtained. According to the defects and the corresponding parameter setting values, a severity level of each of the weak patterns is analyzed. The weak patterns are labeled the severity levels. Machine learning is performed to train a weak pattern severity model.

公开(公告)号：US12052933B2

公开(公告)日：2024-07-30

申请号：US18132992

申请日：2023-04-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jia-Rong Wu ,  Rai-Min Huang ,  I-Fan Chang ,  Ya-Huei Tsai ,  Yu-Ping Wang

IPC: H10N50/80 ,  H10B61/00 ,  H10N50/01

CPC classification number: H10N50/80 ,  H10B61/22 ,  H10N50/01

Abstract: The present invention provides a semiconductor device, the semiconductor device includes a metal interconnection on a substrate, in which a top view of the metal interconnection comprises a quadrilateral; and a magnetic tunneling junction (MTJ) on the metal interconnection, in which a top view of the MTJ comprises a circular shape, an area of the MTJ is smaller than an area of the metal interconnection.