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公开(公告)号:US12035461B2
公开(公告)日:2024-07-09
申请号:US18118915
申请日:2023-03-08
Applicant: SHIN-ETSU CHEMICAL CO., LTD.
Inventor: Toshio Shiobara , Yusuke Taguchi , Ryunosuke Nomura
CPC classification number: H05K1/024 , H05K1/0248 , H05K1/0306 , H05K2201/015 , H05K2201/0175 , H05K2201/0195 , H05K2201/0209
Abstract: A low dielectric substrate for high-speed millimeter-wave communication includes a quartz glass cloth with a dielectric loss tangent of 0.0001 to 0.0015 and a dielectric constant of 3.0 to 3.8 at 10 GHz, and an organic resin with a dielectric loss tangent within 80% to 150% of the dielectric loss tangent of the quartz glass cloth at 10 GHz and a dielectric constant within 50% to 110% of the dielectric constant of the quartz glass cloth at 10 GHz. This provides a low dielectric substrate for high-speed millimeter-wave communication where the low dielectric substrate makes it possible to send signals that are stable and have excellent quality with no difference in propagation time between wirings even if the substrate has an uneven resin distribution and the quartz glass cloth above and below the wirings, and the difference in dielectric loss tangent between members has been reduced to lower transmission loss.
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公开(公告)号:US12035459B2
公开(公告)日:2024-07-09
申请号:US18521587
申请日:2023-11-28
Applicant: CelLink Corporation
Inventor: Kevin Michael Coakley , Malcolm Parker Brown , Dongao Yang , Michael Lawrence Miller , Paul Henry Lego
CPC classification number: H05K1/0201 , H01M50/519 , H05K1/118 , H05K3/007 , H05K3/0073 , H05K3/06 , H05K3/20 , H05K3/281 , H05K3/4623 , H05K3/064 , H05K2201/0145 , H05K2201/015 , H05K2201/0154 , H05K2201/10037 , H05K2203/066 , Y02E60/10 , Y10T29/49156
Abstract: A method of forming a flexible interconnect circuit is described. The method may comprise laminating a substrate to a conductive layer and patterning the conductive layer using a laser while the conductive layer remains laminated to the substrate thereby forming a first conductive portion and a second conductive portion of the conductive layer. The substrate maintains the orientation of the first conductive portion relative to the second conductive portion during and after patterning. The method may also comprise laminating a first insulator to the conductive layer and removing the substrate from the conductive layer such that the first insulator maintains the orientation of the first conductive portion relative to the second conductive portion while and after the substrate is removed. The method may also comprise laminating a second insulator to the second side of the conductive layer while the first insulator remains laminated to the substrate.
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公开(公告)号:US11911954B2
公开(公告)日:2024-02-27
申请号:US16088926
申请日:2017-03-27
Applicant: SOLVAY SPECIALTY POLYMERS USA, LLC
Inventor: Nancy J. Singletary , Stéphane Jeol
IPC: B29C64/00 , B29C64/118 , B29C64/321 , B29C64/364 , B29C64/232 , B29C64/245 , B29C64/295 , B29C64/209 , B29C64/236 , B29C64/40 , B22F12/00 , B05D5/08 , B29C64/176 , B33Y99/00 , B33Y40/00 , B29C64/182 , B33Y40/20 , B22F10/00 , B33Y40/10 , B29C64/205 , B29C64/20 , B22F10/85 , B29C64/10 , B29C64/227 , B29C64/25 , B29C64/30 , B33Y50/02 , B01D67/00 , B29C64/255 , B33Y50/00 , B29C64/307 , B22F12/82 , B33Y80/00 , B29C64/386 , B29C64/393 , B33Y10/00 , B33Y30/00 , B33Y70/00 , B29K69/00 , G03F7/00
CPC classification number: B29C64/118 , B01D67/00045 , B01D67/00415 , B05D5/083 , B22F10/00 , B22F10/85 , B22F12/00 , B22F12/82 , B29C64/00 , B29C64/10 , B29C64/176 , B29C64/182 , B29C64/20 , B29C64/205 , B29C64/209 , B29C64/227 , B29C64/232 , B29C64/236 , B29C64/245 , B29C64/25 , B29C64/255 , B29C64/295 , B29C64/30 , B29C64/307 , B29C64/321 , B29C64/364 , B29C64/386 , B29C64/393 , B29C64/40 , B33Y40/00 , B33Y40/10 , B33Y40/20 , B33Y50/00 , B33Y50/02 , B33Y80/00 , B33Y99/00 , B29K2069/00 , B29K2823/06 , B29K2877/10 , B29K2879/085 , B29K2881/06 , B29K2995/004 , B29K2995/0062 , B33Y10/00 , B33Y30/00 , B33Y70/00 , G03F7/70416 , G03G2215/2054 , G05B2219/49023 , G05B2219/49246 , H05K2201/015 , Y10T156/1722 , Y10T156/1798
Abstract: The invention pertains to a method for manufacturing a three-dimensional object with an additive manufacturing system, such as an extrusion-based additive manufacturing system, a selective laser sintering system, and/or an electrophotography-based additive manufacturing system, comprising providing a support material comprising more than 50% wt. of a semi-crystalline polyamide [polyamide (A)] having a melting point, as determined according to ASTM D3418, of at least 250° C. and possessing a water absorption at saturation, by immersion in water at 23° C., of at least 2% wt.
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公开(公告)号:US11903127B2
公开(公告)日:2024-02-13
申请号:US17381201
申请日:2021-07-21
Applicant: NAN YA PLASTICS CORPORATION
Inventor: Te-Chao Liao , Hao-Sheng Chen , Chih-Kai Chang , Hung-Yi Chang
CPC classification number: H05K1/0366 , B32B27/12 , B32B27/20 , B32B27/322 , B32B2250/03 , B32B2250/24 , B32B2250/40 , B32B2264/101 , B32B2264/104 , B32B2264/107 , B32B2264/301 , B32B2457/08 , H05K2201/015 , H05K2201/0275
Abstract: A fluoride-based resin prepreg and a circuit substrate using the same are provided. The fluoride-based resin prepreg includes 100 PHR of a fluoride-based resin and 20 to 110 PHR of an inorganic filler. Based on a total weight of the fluoride-based resin, the fluoride-based resin includes 10 to 80 wt % of polytetrafluoroethylene (PTFE), 10 to 50 wt % of fluorinated ethylene propylene (FEP), and 0.1 to 40 wt % of perfluoroalkoxy alkane (PFA). The circuit substrate includes a fluoride-based resin substrate and a circuit layer that is formed on the fluoride-based resin substrate.
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公开(公告)号:US11845219B2
公开(公告)日:2023-12-19
申请号:US16864522
申请日:2020-05-01
Inventor: Theodore H. Fedynyshyn , Jennifer A. Lewis , Bradley P. Duncan
IPC: B29C64/00 , B29C64/165 , B29C64/209 , B05D5/08 , C09D5/24 , H01L23/498 , H01B1/00 , G03G5/05 , G03G5/07 , H01M10/653 , H01M4/66 , H05K1/09 , B33Y10/00 , B33Y30/00 , B33Y70/00 , B33Y80/00 , B29K23/00 , B29K25/00 , B29K105/00 , B29L31/34 , G01N33/00
CPC classification number: B29C64/165 , B05D5/083 , B29C64/209 , C09D5/24 , G03G5/05 , G03G5/07 , H01B1/00 , H01L23/49883 , H01M4/663 , H01M10/653 , H05K1/092 , B29K2023/06 , B29K2023/12 , B29K2025/06 , B29K2105/251 , B29K2995/0006 , B29K2995/0008 , B29K2995/0088 , B29K2995/0093 , B29K2995/0094 , B29L2031/3456 , B33Y10/00 , B33Y30/00 , B33Y70/00 , B33Y80/00 , G01N2033/0095 , H05K2201/015 , H05K2201/03
Abstract: A 3-D printed device comprising one or more structures, the structures comprising a plurality of magnetically responsive particles and one or more diblock or triblock copolymers; the diblock or triblock copolymers having an A-B, A-B-A, or A-B-C block-type structure in which the A-blocks and C-blocks are an aromatic-based polymer or an acrylate-based polymer and the B-blocks are an aliphatic-based polymer. These 3-D printed devices may be formed using a method that comprises providing a magnetic ink composition; applying the magnetic ink composition to a substrate in a 3-D solvent cast printing process to form one or more structures; and drying the one or more structures formed from the magnetic ink composition. The dried structures can exhibit one or more regions of magnetic permeability greater than 1.3×10−6 H/m.
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公开(公告)号:US11840047B2
公开(公告)日:2023-12-12
申请号:US16783909
申请日:2020-02-06
Applicant: TAIWAN UNION TECHNOLOGY CORPORATION
Inventor: Shi-Ing Huang , Shur-Fen Liu , Kai-Hsiang Lin
IPC: B32B15/14 , B32B5/02 , B32B15/20 , B32B27/12 , H05K1/03 , B32B27/20 , H05K3/02 , B32B27/32 , B32B27/30
CPC classification number: B32B15/14 , B32B5/02 , B32B15/20 , B32B27/12 , B32B27/20 , B32B27/304 , B32B27/322 , H05K1/036 , H05K3/022 , B32B2250/05 , B32B2250/40 , B32B2260/021 , B32B2260/046 , B32B2262/101 , B32B2264/102 , B32B2307/204 , B32B2457/08 , H05K2201/015 , H05K2201/0191 , H05K2201/0195
Abstract: A metal-clad laminate, a printed circuit board using the same and a method for manufacturing the metal-clad laminate. The metal-clad laminate comprises:
a first dielectric layer, comprising a first dielectric material and not comprising a reinforcing fabric, the first dielectric material comprising 20 wt % to 60 wt % of a first fluoropolymer and 40 wt % to 80 wt % of a first filler;
a second dielectric layer disposed on one side of the first dielectric layer and comprising a reinforcing fabric and a second dielectric material formed on the surface of the reinforcing fabric, wherein the thickness of the reinforcing fabric is not higher than 65 μm and the second dielectric material comprises 55 wt % to 100 wt % of a second fluoropolymer and 0 to 45 wt % of a second filler; and
a metal foil disposed on the other side of the second dielectric layer that is opposite to the first dielectric layer.-
公开(公告)号:US20230232538A1
公开(公告)日:2023-07-20
申请号:US18010050
申请日:2021-06-25
Inventor: Toshiki IWASAKI , Makoto NAKABAYASHI , Satoshi KIYA
CPC classification number: H05K3/022 , H05K1/0366 , H05K1/036 , H05K2201/015
Abstract: A substrate for a printed wiring board includes a base layer, and a copper foil directly or indirectly stacked on at least a part of one or both surfaces of the base layer. The base layer includes a matrix containing a fluororesin as a main component and one or more reinforcing material layers included in the matrix, and a ratio B/A is 0.003 to 0.37, where A is an average thickness of the base layer, and B is an average distance between a surface of the copper foil facing the matrix and a surface of a reinforcing material layer closest to the surface of the copper foil facing the copper foil.
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公开(公告)号:US20190141833A1
公开(公告)日:2019-05-09
申请号:US16238586
申请日:2019-01-03
Applicant: AGC Inc.
Inventor: Tomoya HOSODA , Tatsuya TERADA
CPC classification number: H05K1/0373 , H01P3/00 , H01Q1/38 , H05K1/024 , H05K1/0393 , H05K1/115 , H05K3/422 , H05K3/427 , H05K2201/015 , H05K2201/0154 , H05K2201/0212 , H05K2203/072 , H05K2203/0776 , H05K2203/0779 , H05K2203/095
Abstract: To provide a wiring substrate having excellent transmission characteristics, of which initial failure of a plating layer formed on an inner wall surface of a hole is suppressed regardless of the type of the pre-treatment applied to the inner wall surface of the hole, and of which the plating layer has favorable heat resistance, and a process for producing it.A wiring substrate 10 comprising an electrical insulator layer 20, a first conductor layer 32 formed on a first surface of the electrical insulator layer 20, a second conductor layer 34 formed on a second surface of the electrical insulator layer 20, and a plating layer 42 provided on an inner wall surface of a hole 40 which opens from the first conductor layer 32 through the second conductor layer 34; wherein the electrical insulator layer 20 has a heat resistant resin layer 22 containing a heat resistant resin and a resin powder; the resin powder is formed from a resin material containing a melt-formable fluororesin having a functional group such as a carbonyl group-containing group; the content of the resin powder is from 5 to 70 mass % to the heat resistant resin layer 22; and the electrical insulator layer 20 has a dielectric constant of from 2.0 to 3.5.
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公开(公告)号:US20180332720A1
公开(公告)日:2018-11-15
申请号:US16031748
申请日:2018-07-10
Applicant: Amphenol Corporation
Inventor: Arthur E. Harkness, JR. , Eva M. Kenny-McDermott , Paul W. Farineau , Raymond A. Lavallee , Michael Fancher
IPC: H05K3/46 , H05K3/22 , H05K3/38 , H05K1/02 , H05K1/11 , H05K3/00 , H05K1/09 , H05K1/03 , H05K3/20
CPC classification number: H05K3/4632 , H05K1/0242 , H05K1/0326 , H05K1/034 , H05K1/0346 , H05K1/0366 , H05K1/0373 , H05K1/09 , H05K1/111 , H05K1/115 , H05K1/116 , H05K3/0073 , H05K3/202 , H05K3/22 , H05K3/38 , H05K3/382 , H05K3/383 , H05K3/384 , H05K3/385 , H05K3/388 , H05K3/389 , H05K3/4658 , H05K3/4685 , H05K2201/0145 , H05K2201/015 , H05K2201/0154 , H05K2201/0158 , H05K2201/0209 , H05K2201/0212 , H05K2203/1194
Abstract: High-speed interconnects for printed circuit boards and methods for forming the high-speed interconnects are described. A high-speed interconnect may comprise a region of a conductive film having a reduced surface roughness and one or more regions that have been treated for improved bonding with an adjacent insulating layer. Regions of reduced roughness may be used to carry high data rate signals within PCBs. Regions treated for bonding may include a roughened surface, adhesion-promoting chemical treatment, and/or material deposited to improve wettability of the surface and/or adhesion to a cured insulator.
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公开(公告)号:US20180061521A1
公开(公告)日:2018-03-01
申请号:US15789402
申请日:2017-10-20
Applicant: Chasm Technologies, Inc.
Inventor: Robert F. Praino, JR. , Sean P. Arthur , David J. Arthur
CPC classification number: H01B1/24 , B32B5/02 , B32B7/02 , B32B15/02 , B32B15/08 , B32B15/20 , B32B27/20 , B32B2305/10 , B32B2305/30 , B32B2307/202 , B32B2307/40 , B32B2311/08 , B32B2311/12 , B32B2313/04 , B32B2457/00 , B32B2551/00 , B82Y10/00 , C08K3/041 , C08K3/08 , C08K2003/0806 , C09D5/24 , C09D7/61 , C09D11/52 , H01B1/026 , H01B1/22 , H05K1/095 , H05K1/097 , H05K2201/0108 , H05K2201/0145 , H05K2201/015 , H05K2201/026 , H05K2201/0323 , C08L39/06 , C08L27/18
Abstract: A transparent conductive film (10) that has a substrate (14) having a surface (14a, 14b), a nanowire layer (12, 12a) over one or more portions of the surface (14a, 14b) of the substrate (14), and a conductive layer (16, 16a) on the portions comprising the nanowire layer (12, 12a), the conductive layer (16, 16a) comprising carbon nanotubes (CNT) and a binder.
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